The problem to be solved by the invention is to provide a laminate capable of effectively enhancing thermal conductivity and adhesiveness, in spite of the relatively large thickness of a patterned metal layer. The laminate (1) according to the present invention includes a metal substrate (4), an insulating layer (2) laminated on one surface of the metal substrate (4), and a patterned metal layer (3) laminated on the surface of the insulating layer (2) on the side opposite to the metal substrate (4), the metal layer (3) is 300 μm or more in thickness, and the insulating layer (2) includes boron nitride (12) and an inorganic filler (13) other than boron nitride.

Compliant interconnect based on deformable wires compressed against contacts on chip scale packages (CSP). Including deformable rubbery overcoat on at least one of the CSP. The use of substantially optically transmitting overcoat means to secure the assembly is also disclosed. The use of various wires including but not limited to gold, silver, aluminum, carbon nanotube yarns, and composite wires also disclosed.

The problem to be solved by the invention is to provide a laminate capable of effectively enhancing thermal conductivity and adhesiveness, in spite of the relatively large thickness of a patterned metal layer. The laminate (1) according to the present invention includes a metal substrate (4), an insulating layer (2) laminated on one surface of the metal substrate (4), and a patterned metal layer (3) laminated on the surface of the insulating layer (2) on the side opposite to the metal substrate (4), the metal layer (3) is 300 m or more in thickness, and the insulating layer (2) includes boron nitride (12) and an inorganic filler (13) other than boron nitride.

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

A first conductive feature of a first substrate is bonded to a second conductive feature of a second substrate. The first conductive feature is formed by depositing a conductive base layer on the first substrate, the first substrate having an opening formed therein, recessing the conductive base layer in the opening, and depositing a conductive surface layer on the recessed conductive base layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive feature and the second conductive feature.

A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

A package apparatus comprises a first wiring layer, a metal layer, a conductive pillar layer, a passive component, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to each other. The metal layer is disposed on the first surface of the first wiring layer. The conductive pillar layer is disposed on the second surface of the first wiring layer. The passive component is disposed on the second surface of the first wiring layer. The first molding compound layer is disposed within a part of the zone of the first wiring layer and the conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.