In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

A semiconductor package includes a leadframe having a clip foot portion, the clip foot portion having a first tie bar, a conductive clip situated over the leadframe, the conductive clip including a first lock fork having at least two prongs around the first tie bar so as to secure the conductive clip to the clip foot portion of the leadframe. The conductive clip includes a second lock fork having at least two prongs around a second tie bar of the clip foot portion. The conductive clip is electrically coupled to the clip foot portion of the leadframe. The clip foot portion of the leadframe includes exposed leads. The semiconductor package also includes at least one semiconductor device situated on the leadframe. The at least one semiconductor device is coupled to a driver integrated circuit situated on the leadframe.

According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.

Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.

A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively; and (c) forming an insulator layer on the first surface of the metal substrate to encapsulate the die and the die contacts after step (b).

An electronic device includes: a heating element; an insulation metal component; and a sealing component. The insulation metal component includes a first metal part to which the heating element is mounted, a second metal part having a portion exposed from the sealing component, and an insulation part interposed between the first metal part and the second metal part. The second metal part has a central part and a peripheral part having a thickness thinner than that of the central part. The second metal part has one surface opposing and in tight contact with the insulation part, and an exposed surface opposite from the sealing component within an area corresponding to the central part. The second metal part has a recess recessed from a virtual straight line that connects an end of the one surface to an end of the exposed surface at a shortest distance around the central part.

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.