A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

A semiconductor package includes a bottom package having a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die has an active surface and a rear surface coupled to the top surface of the substrate. The semiconductor die comprises through silicon vias. A top package is stacked on the bottom package. The top package comprises a memory component. A middle re-distribution layer (RDL) structure is disposed between the top package and the bottom package. The active surface of the semiconductor die is directly connected to the middle RDL structure through connecting elements. The memory component is electrically connected to the substrate via the interconnect structures of the middle RDL structure and the through silicon vias of the semiconductor die.

The present application discloses a semiconductor device with a re-fill layer. The semiconductor device includes a chip stack including a first base die; a first stacked die positioned on a front surface of the first base die; and a re-fill layer positioned on a sidewall of the stacked die. The re-fill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide, or hafnium oxide.

A method for fabricating a semiconductor device includes providing a base wafer comprising a scribing portion; bonding a first stacked die and a second stacked die onto a front surface of the base wafer through a hybrid bonding process; conformally forming a re-fill layer to cover the first stacked die and the second stacked die; forming a first molding layer to cover the re-fill layer and configure an intermediate semiconductor device comprising the base wafer, the first stacked die, the second stacked die, the re-fill layer, and the first molding layer; and dicing the intermediate semiconductor device along the scribing portion to separate the first stacked die and the second stacked die, the re-fill layer, the first molding layer, and the base wafer.

A method for fabricating a semiconductor device includes providing a base wafer comprising a scribing portion; bonding a first stacked die and a second stacked die onto a front surface of the base wafer through a hybrid bonding process; conformally forming a re-fill layer to cover the first stacked die and the second stacked die; forming a first molding layer to cover the re-fill layer and configure an intermediate semiconductor device comprising the base wafer, the first stacked die, the second stacked die, the re-fill layer, and the first molding layer; and dicing the intermediate semiconductor device along the scribing portion to separate the first stacked die and the second stacked die, the re-fill layer, the first molding layer, and the base wafer.

Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures.

A semiconductor device configures one arm of an upper-lower arm circuit, and includes: a semiconductor element that includes a first main electrode and a second main electrode, wherein a main current between the first main electrode and the second main electrode; and multiple main terminals that include a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode. The first main terminal and the second main terminal are placed adjacent to each other; A lateral surface of the first main terminal and a lateral surface of the second main terminal face each other in one direction orthogonal to a thickness direction of the semiconductor element.

A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.

A semiconductor apparatus that ensures heat dissipation using a heat dissipating member with multiple fins formed by folding a metal plate, a manufacturing method for the semiconductor apparatus, and a power converter are obtained. The semiconductor device is bonded to a lead frame. The lead frame is provided on an insulating layer and a metal base plate is provided on the face opposite to the face of the insulating layer on which the semiconductor device is bonded. The semiconductor device, the lead frame, the insulating layer, and the metal base plate are sealed with a sealing member in such a way that a portion of the lead frame and a portion of the metal base plate are exposed. The exposed portion of the metal base plate exposed from the sealing member is inserted in an opening of a support frame. A heat dissipating member is bonded to both the metal base plate and the support frame.