Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 μm; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2μm; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating dotted diffusion, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed in a plurality of non-continuous trenches in the back surface of the substrate.

Disclosed is a tandem solar cell according to an aspect including: a silicon lower cell; a perovskite upper cell disposed on the silicon lower cell; and a bonding layer for bonding the silicon lower cell and the perovskite upper cell between the silicon lower cell and the perovskite upper cell, wherein the front surface portion of the silicon lower cell being in contact with the bonding layer includes a texture structure, the bonding layer includes a first transparent electrode layer formed on the sidewall of the texture structure, a buried layer filling concave portions of the texture structure on the first transparent electrode layer, and a second transparent electrode layer on top surfaces of the buried layer, the first transparent electrode layer and the texture structure.

Discussed is a solar cell including a first conductive region positioned at a front surface of a semiconductor substrate and containing impurities of a first conductivity type or a second conductivity type, a second conductive region positioned at a back surface of the semiconductor substrate and containing impurities of a conductivity type opposite a conductivity type of impurities of the first conductive region, a first electrode positioned on the front surface of the semiconductor substrate and connected to the first conductive region, and a second electrode positioned on the back surface of the semiconductor substrate and connected to the second conductive region. Each of the first and second electrodes includes metal particles and a glass frit.

Disclosed is an opto-electronic device including a semiconducting substrate, a layered interface including at least one layer, the layered interface having a first surface in contact with a surface of the semiconducting substrate and the layered interface being adapted for passivating the surface of the semiconducting substrate, the layered interface having a second surface and the layered interface being adapted for electrically insulating the first surface from the second surface, and a textured surface structure including a plurality of nanowires and a transparent dielectric coating, the textured surface structure being in contact with the second surface of the layered interface, the plurality of nanowires protruding from the second surface and the plurality of nanowires being embedded between the second surface and the transparent dielectric coating.

Disclosed is an opto-electronic device including a semiconducting substrate, a layered interface including at least one layer, the layered interface having a first surface in contact with a surface of the semiconducting substrate and the layered interface being adapted for passivating the surface of the semiconducting substrate, the layered interface having a second surface and the layered interface being adapted for electrically insulating the first surface from the second surface, and a textured surface structure including a plurality of nanowires and a transparent dielectric coating, the textured surface structure being in contact with the second surface of the layered interface, the plurality of nanowires protruding from the second surface and the plurality of nanowires being embedded between the second surface and the transparent dielectric coating.

A photovoltaic device includes: a silicon substrate having a front surface having a texture; and an amorphous silicon layer having an uneven surface corresponding to the texture, wherein the amorphous silicon layer is amorphous in peak portions and slope portions extending between the peak portions and valley portions of the uneven surface, and has crystalline regions which grow, in a pillar manner, approximately perpendicularly from a substrate surface of the silicon substrate in the valley portions, the crystalline regions being discretely present along upper ends of the valley portions, the upper ends being opposite lower ends of the valley portions, the lower ends being in contact with the silicon substrate, wherein coverage of the crystalline regions in the valley portions is higher than coverage of amorphous regions in the valley portions.

A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. Each nanopillar includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer have different conductivity types. The method also includes forming a graphene layer overlying the plurality of nanopillars. The graphene layer is connected to each of the plurality of nanopillars.

The present invention relates to a chalcogenide device and particularly to a metal chalcogenide device using transition metal chalcogenides as electrodes and a production method therefor. The metal chalcogenide device according to the present invention may comprise: a substrate; an oxide layer positioned on the substrate; a first conductive metal chalcogenide layer positioned on the oxide layer; and first and second electrodes, which are positioned apart from one another on the metal chalcogenide layer and comprise metal chalcogenides.