H01L31/0352

Semiconductor Structures
20230051827 · 2023-02-16 ·

A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

PHOTODIODE FOR WEARABLE DEVICES
20230051794 · 2023-02-16 ·

The present invention provides a photodiode for a wearable sensor system, the photodiode having a rectangular active area sensitive to wavelengths within the spectral range of 1200 nm to 2400 nm. The present invention also provides a wearable sensor system comprising the photodiode.

Method of facilitating straining of a semiconductor element for semiconductor fabrication, semiconductor platform obtained by the method, and optoelectronic device comprising the semiconductor platform

Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

Solar cell emitter region fabrication with differentiated P-type and N-type architectures and incorporating dotted diffusion

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating dotted diffusion, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed in a plurality of non-continuous trenches in the back surface of the substrate.

Photodiode and/or pin diode structures with one or more vertical surfaces

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

Optical sensor and method for manufacturing same
11581445 · 2023-02-14 · ·

An optical sensor includes a graphene layer, a first electrode and a second electrode that are connected to the graphene layer, and an enhancement layer. The enhancement layer is disposed below the graphene layer to enhance the intensity of an optical electric field by surface plasmon resonance. The first electrode and the second electrode are arranged parallel to a first direction. The intensity of the optical electric field enhanced by the enhancement layer is greater on a first electrode side than on a second electrode side with respect to a centerline in the first direction of the graphene layer.

Radiation Hardened Infrared Focal Plane Array
20230008594 · 2023-01-12 ·

An FPA includes a substrate; a plurality of spaced-apart implant regions deposited in the substrate; a plurality of supplemental metal contacts, one supplemental metal contact of the plurality of supplemental metal contacts electrically connected to one implant region of the plurality of implant regions; a plurality of metal conductors electrically connecting the plurality of supplemental metal contacts; and a primary metal contact, electrically connected to the plurality of supplemental metal contacts by at least one of the metal conductors of the plurality of metal conductors. The pixel can include an Indium bump electrically connected to the primary metal contact.

Radiation Hardened Infrared Focal Plane Array
20230008594 · 2023-01-12 ·

An FPA includes a substrate; a plurality of spaced-apart implant regions deposited in the substrate; a plurality of supplemental metal contacts, one supplemental metal contact of the plurality of supplemental metal contacts electrically connected to one implant region of the plurality of implant regions; a plurality of metal conductors electrically connecting the plurality of supplemental metal contacts; and a primary metal contact, electrically connected to the plurality of supplemental metal contacts by at least one of the metal conductors of the plurality of metal conductors. The pixel can include an Indium bump electrically connected to the primary metal contact.

3D MICRO DISPLAY DEVICE AND STRUCTURE
20230038149 · 2023-02-09 · ·

A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer; a third level including a second plurality of light emitting diodes (LEDs), the second plurality of LEDs including a third single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

3D MICRO DISPLAY DEVICE AND STRUCTURE
20230038149 · 2023-02-09 · ·

A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer; a third level including a second plurality of light emitting diodes (LEDs), the second plurality of LEDs including a third single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.