Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.

Methods and devices for an avalanche photo-transistor. In one aspect, an avalanche photo-transistor includes a detection region configured to absorb light incident on a first surface of the detection region and generate one or more charge carriers in response, a first terminal in electrical contact with the detection region and configured to bias the detection region, an interim doping region, a second terminal in electrical contact with the interim doping region and configured to bias the interim doping region, a multiplication region configured to receive the one or more charge carriers flowing from the interim doping region and generate one or more additional charge carriers in response, a third terminal in electrical contact with the multiplication region and configured to bias the multiplication region, wherein the interim doping region is located in between the detection region and the multiplication region.

A lateral interband Type II engineered (LITE) detector is provided. LITE detectors use engineered heterostructures to spatially separate electrons and holes into separate layers. The device may have two configurations, a positive intrinsic (PIN) configuration and a BJT (Bipolar junction transistor) configuration. The PIN configuration may have a wide bandgap (WBG) layer that transports the holes above a narrow bandgap (NBG) absorber layer that absorbs the target radiation and transports the electrons. The BJT configuration may have a WBG layer operating as a BJT above an NBG layer. In both configurations, the LITE design uses a Type II staggered offset between the NBG layers and the WBG layers that provides a built-in field for the holes to drift from an absorber region to a transporter region.

A photo detector having a substrate and a first structure formed on the substrate. The first structure includes an emitter layer formed on the substrate and a base layer formed on the emitter layer. Further, the first structure includes a collector layer formed on the base layer. The collector layer has a plasmonic structure. The plasmonic structure includes a first plurality of mesa structures. Each of the mesa structures of the first plurality of mesa structures includes a second plurality of mesa structures having ridges arranged in a regularly repeating pattern.

Methods and devices for an avalanche photo-transistor. In one aspect, an avalanche photo-transistor includes a detection region configured to absorb light incident on a first surface of the detection region and generate one or more charge carriers in response, a first terminal in electrical contact with the detection region and configured to bias the detection region, an interim doping region, a second terminal in electrical contact with the interim doping region and configured to bias the interim doping region, a multiplication region configured to receive the one or more charge carriers flowing from the interim doping region and generate one or more additional charge carriers in response, a third terminal in electrical contact with the multiplication region and configured to bias the multiplication region, wherein the interim doping region is located in between the detection region and the multiplication region.

An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.

In described examples, an integrated circuit includes a leadframe structure, which includes electrical conductors. A first coil structure is electrically connected to a first pair of the electrical conductors of the leadframe structure. The first coil structure is partially formed on a semiconductor die structure. A second coil structure is electrically connected to a second pair of the electrical conductors of the leadframe structure. The second coil structure is partially formed on the semiconductor die structure. A molded package structure encloses portions of the leadframe structure. The molded package structure exposes portions of the first and second pairs of the electrical conductors to allow external connection to the first and second coil structures. The molded package structure includes a cavity to magnetically couple portions of the first and second coil structures.

A phototransistor includes an emitter, a collector, and a base between the emitter and the collector. The base has a thickness greater than 500 nanometers and the base absorbs photons passing through the collector to the base.

Disclosed is an active photonic device having a Darlington configuration with a substrate and a collector layer that is over the substrate. The collector layer includes an inner collector region. An outer collector region substantially surrounds the inner collector region and is spaced apart from the inner collector region. A base layer is over the collector layer. A first outer base region and a second outer base region substantially surround the inner base region and are spaced apart from the inner base region and each other. An emitter layer is over the base layer. The emitter layer includes an inner emitter region that is ring-shaped and resides over and extends substantially around an outer periphery of the inner base region. A first outer emitter region and a second outer emitter region substantially surround the inner emitter region and are spaced apart from the inner emitter region and each other.

Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.