A PIN device includes: a first doped layer, a second doped layer, and an intrinsic layer between the first doped layer and the second doped layer, where the second doped layer includes a body portion and an electric field isolating portion at least partially enclosing the body portion; and the electric field isolating portion is doped differently from the body portion.

A PIN device includes: a first doped layer, a second doped layer, and an intrinsic layer between the first doped layer and the second doped layer, where the second doped layer includes a body portion and an electric field isolating portion at least partially enclosing the body portion; and the electric field isolating portion is doped differently from the body portion.

An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

Disclosed is a photosensitive component, including: an intrinsic layer; a first doped layer provided on a light incident side of the intrinsic layer; and a second doped layer provided on a light exit side of the intrinsic layer; the intrinsic layer, the first doped layer and the second doped layer are all doped with a dopant, and silicon ions are injected into the intrinsic layer, the first doped layer and the second doped layer. An X-ray detector and a display device are further disclosed.

Disclosed is a photosensitive component, including: an intrinsic layer; a first doped layer provided on a light incident side of the intrinsic layer; and a second doped layer provided on a light exit side of the intrinsic layer; the intrinsic layer, the first doped layer and the second doped layer are all doped with a dopant, and silicon ions are injected into the intrinsic layer, the first doped layer and the second doped layer. An X-ray detector and a display device are further disclosed.

A charged particle beam system may include a detector. A package for a detector may have a package body that includes two sets of pins, each of the sets of pins including two pins. Each pin of the sets of pins may be configured to be connected to one of two terminals of a sensing element. Pins of different sets may be configured to be connected to a different one of the two terminals of the diode. The sets of pins may be arranged with a symmetry such that magnetic fields generated when current passes through the sets of pins is reduced due to the symmetry.

A charged particle beam system may include a detector. A package for a detector may have a package body that includes two sets of pins, each of the sets of pins including two pins. Each pin of the sets of pins may be configured to be connected to one of two terminals of a sensing element. Pins of different sets may be configured to be connected to a different one of the two terminals of the diode. The sets of pins may be arranged with a symmetry such that magnetic fields generated when current passes through the sets of pins is reduced due to the symmetry.

A thin film transistor array substrate for a digital X-ray detector device includes a p+ type semiconductor layer and a p− type semiconductor layer having different impurity concentrations are disposed above an intrinsic semiconductor layer of the PIN diode and an n+ type semiconductor layer and an n− type semiconductor layer having different impurity concentrations are disposed below the intrinsic semiconductor layer of the PIN diode to minimize ejection of holes by the p− type semiconductor layer and minimize ejection of electros by the n− type semiconductor layer, thereby minimizing occurrence of leakage current of the PIN diode.

A thin film transistor array substrate for a digital X-ray detector device including a base substrate; a plurality of data lines and a plurality of gate lines disposed on the base substrate and arranged to cross each other; a driving thin film transistor disposed above the base substrate and including a first electrode, a second electrode, a gate electrode and an active layer; a PIN diode connected to the driving thin film transistor; and at least one shielding layers disposed above the driving thin film transistor and configured to overlay the active layer, wherein the at least one shielding layers are electrically connected to the plurality of data lines.