A structure of the avalanche photodiode type includes a first P doped semiconducting zone, a second multiplication semiconducting zone adapted to supply a multiplication that is preponderant for electrons, a fourth P doped semiconducting “collection” zone. One of the first and second semiconducting zones forms the absorption zone. The structure also includes a third semiconducting zone formed between the second semiconducting zone and the fourth semiconducting zone. The third semiconducting zone has an electric field in operation capable of supplying an acceleration of electrons between the second semiconducting zone and the fourth semiconducting zone without multiplication of carriers by impact ionisation.

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

Disclosed herein is a method for making a radiation detector. The method comprises forming a recess into a substrate and forming a semiconductor single crystal in the recess. The semiconductor single crystal may be a cadmium zinc telluride (CdZnTe) single crystal or a cadmium telluride (CdTe) single crystal. The method further comprises forming electrical contacts on the semi conductor single crystal and bonding the substrate to another substrate comprising an electronic system therein or thereon. The electronic system is connected to the electrical contact of the semiconductor single crystal and configured to process an electrical signal generated by the semiconductor single crystal upon absorption of radiation particles.

An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg.sub.1-xCd.sub.xTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

An electrical device includes a substrate with a compressive layer, a neutral stress buffer layer and a tensile stress compensation layer. The stress buffer layer and the stress compensation layer may each be formed with aluminum nitride using different processing parameters to provide a different intrinsic stress value for each layer. The aluminum nitride tensile layer is configured to counteract stresses from the compressive layer in the device to thereby control an amount of substrate bow in the device. This is useful for protecting fragile materials in the device, such as mercury cadmium telluride. The aluminum nitride stress compensation layer also can compensate for forces, such as due to CTE mismatches, to protect the fragile layer. The device may include temperature-sensitive materials, and the aluminum nitride stress compensation layer or stress buffer layer may be formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

A photovoltaic device (100) can include an absorber layer (160). The absorber layer (160) can be doped p-type with a Group V dopant and can have a carrier concentration of the Group V dopant greater than 4×10.sup.15 cm.sup.−3. The absorber layer (160) can include oxygen in a central region of the absorber layer (160). The absorber layer (160) can include an alkali metal in the central region of the absorber layer (160). Methods for carrier activation can include exposing an absorber layer (160) to an annealing compound in a reducing environment (220). The annealing compound (224) can include cadmium chloride and an alkali metal chloride.

Embodiments of a photovoltaic device are provided herein. The photovoltaic device can include a layer stack and an absorber layer disposed on the layer stack. The absorber layer can include a first region and a second region. Each of the first region of the absorber layer and the second region of the absorber layer can include a compound comprising cadmium, selenium, and tellurium. An atomic concentration of selenium can vary across the absorber layer. The first region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. The second region of the absorber layer can have a thickness between 100 nanometers to 3000 nanometers. A ratio of an average atomic concentration of selenium in the first region of the absorber layer to an average atomic concentration of selenium in the second region of the absorber layer can be greater than 10.

A radiation detection probe and a manufacturing method therefor, and a radiation detection chip. The method comprises: simulating each of a plurality of cadmium zinc telluride crystals having different three-dimensional sizes; obtaining the radiation response characteristics of each cadmium zinc telluride crystal; according to the radiation response characteristics, selecting a specific cadmium zinc telluride crystal from the plurality of cadmium zinc telluride crystals, wherein the specific cadmium zinc telluride crystal is a cadmium zinc telluride crystal having optimal performance indexes corresponding to the radiation response characteristics in the plurality of cadmium zinc telluride crystals; and configuring a first electrode and a second electrode for the specific cadmium zinc telluride crystal so as to constitute the radiation detection probe.

The present invention proposes a method to form a CdSeTe thin film with a defined amount of selenium and with a high quality. The method comprises the steps of providing a base substrate and of depositing a partial CdSeTe layer on a first portion of the base substrate. The step of depositing a partial CdSeTe layer is performed at least twice, wherein a predetermined time period without deposition of a partial CdSeTe layer on the first portion of the base substrate is provided between two subsequent steps of depositing a partial CdSeTe layer. The temperature of the base substrate and the CdSeTe layer already deposited on the first portion of the base substrate is controlled during the predetermined time period such that re-evaporation of Cd and/or Te from the CdSeTe layer already deposited takes place.