A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

The disclosure relates to a micro component structure and a manufacturing method thereof, and a transfer method for a light-emitting diode (LED) chip. The micro component structure includes a substrate (300), multiple stacked adhesive layer structures spaced on a first surface (300a) of the substrate (300), and multiple LED chips (20) correspondingly disposed on the multiple stacked adhesive layer structures. Each of the multiple LED chips (20) has two extraction electrodes (21) at a surface facing toward the multiple stacked adhesive layer structures. Each of the multiple stacked adhesive layer structures includes a photolysis adhesive layer (31′) and a pyrolysis adhesive layer (32′) that are stacked. The photolysis adhesive layer (31′) is in contact with the first surface (300a). The pyrolysis adhesive layer (32′) is located between the two extraction electrodes (21) and has a thickness greater than a height of each of the two extraction electrodes (21).

A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elements and/or active elements, the interface being produced on the surface of a second silicon-based substrate; removing the first silicon-based substrate and the at least elementary base layer located on the elementary structure.

A bonded semiconductor device including an epitaxial layer, and a support substrate made of a material different from that of the epitaxial layer and bonded to the epitaxial layer. Any one of the epitaxial layer and the support substrate has a bonding surface with a radial pattern including recesses or protrusions radially spreading from a certain point on the bonding surface as a center.

Methods of fabricating single photon emitters (SPEs) including nanoindentation of hexagonal boron nitride (hBN) host materials and annealing thereof, devices formed from such methods, and chips with a single photon emitter. A substrate with a layer of hBN is provided. Nanoindentation is performed on the layer of hBN to produce an array of sub-micron indentations in the layer of hBN. The layer of hBN is annealed to activate SPEs near the indentations. Devices include a substrate with an SPE produced in accordance with the methods. Chips include a substrate, an hBN layer, and an SPE including an indentation on the hBN layer, in which the substrate is not damaged at the indentation.

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a subLED electrically connected to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

A device, such as a light-emitting device, e.g. a laser device, comprising: a plurality of group III-V semiconductor NWs grown on one side of a graphitic substrate, preferably through the holes of an optional hole-patterned mask on said graphitic substrate; a first distributed Bragg reflector or metal mirror positioned substantially parallel to said graphitic substrate and positioned on the opposite side of said graphitic substrate to said NWs; optionally a second distributed Bragg reflector or metal mirror in contact with the top of at least a portion of said NWs; and wherein said NWs comprise aim-type doped region and a p-type doped region and optionally an intrinsic region there between.

A semiconductor structure comprises an n-doped first layer, a p-doped second layer doped with a first dopant, and an active layer disposed between the n-doped first layer and the p-doped second layer and having at least one quantum well. The active layer of the semiconductor structure is divided into a plurality of first optically active regions, at least one second region, and at least one third region. Here, the plurality of first optically active regions are arranged in a hexagonal pattern spaced apart from each other. The at least one quantum well in the active region comprises a larger band gap in the at least one second region than in the plurality of first optically active regions and the at least one third region, the band gap being modified, in particular, by quantum well intermixing. The at least one second region encloses the plurality of first optically active regions.

A group-III-nitride structure and a manufacturing method thereof are provided. In the manufacturing method, one or more grooves are formed by etching a first group-III-nitride epitaxial layer with a patterned first mask layer as a mask; then a second mask layer is formed at least on one or more bottom walls of the one or more grooves, and a first epitaxial growth is performed on the first group-III-nitride epitaxial layer to laterally grow and form a second group-III-nitride epitaxial layer with the second mask layer as a mask, where the one or more grooves are filled with the second group III-nitride epitaxial layer; a second epitaxial growth is then performed on the second group-III-nitride epitaxial layer to grow and form a third group-III-nitride epitaxial layer on the second group-III-nitride epitaxial layer and the patterned first mask layer.

A method of manufacturing an optoelectronic device including-light-emitting diodes comprising the forming of three-dimensional semiconductor elements made of a III-V compound, each comprising a lower portion and an upper portion and, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor area of the III-V compound covering the active area. The upper portions are formed by vapor deposition at a pressure lower than 1.33 mPa.