A display device includes a pixel electrode disposed on a substrate and including a reflective electrode layer and an upper electrode layer, a contact electrode disposed on the pixel electrode, light-emitting elements disposed on the contact electrode and disposed perpendicular to the pixel electrode, a planarization layer disposed on the pixel electrode, the planarization layer filling a space between the light-emitting elements, and a common electrode disposed on the planarization layer and the light-emitting elements, and a size of the contact electrode is equal to a size of each of the light-emitting elements in a plan view, and the upper electrode layer is disposed on the reflective electrode layer and is in a polycrystalline phase.

A radiation-emitting semiconductor chip may include a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer, a first metallic mirror with which charge carriers can be embedded into the first semiconductor layer, a first metallic contact layer disposed atop the first metallic mirror, and a second metallic contact layer disposed atop the first metallic contact layer. A first seed layer may be disposed between the first metallic contact layer and the first metallic mirror. A second seed layer may be disposed between the first metallic contact layer and the second metallic contact layer. The radiation-emitting semiconductor chip may include a radiation exit face having a multitude of emission regions. The first metallic mirror may have a multitude of cutouts that each define a lateral extent of one of the emission regions.

A light-emitting diode (LED) includes a substrate, an epitaxial structure, and first and second electrodes. The substrate has a surface with upper and lower edges, and two opposing side edges. The epitaxial structure is disposed on the surface. The first and second electrodes are disposed on the epitaxial structure. The second electrode includes a main portion and two extension portions. A projection of each of the extension portions on the surface extends in an extension direction away from the lower edge toward a corresponding one of the side edges in such a manner that an included angle between an central axis perpendicular to the bottom edge and a tangent line of any point on the projection of the extension portions on the surface is not greater than 90° and increases along the extension direction.

A light emitting diode package includes: a housing including a cavity region therein; a light emitting diode chip mounted in the cavity region of the housing; and a resin part formed in the cavity region to cover a light emitting surface of the light emitting diode chip. The housing includes a first surface and a second surface perpendicular to a width direction of the housing and spaced apart from each other, and a third surface and a fourth surface perpendicular a longitudinal direction of the housing and spaced apart from each other, in which the first surface and the second surface surround the resin part while the third surface and the fourth surface expose side surfaces of the resin part.

Photo-emitting and/or photo-receiving diode array device, comprising: a stack of first and second semiconductor layers doped according to different types; first trenches passing through the stack and surrounding a region of the stack wherein several diodes are formed; dielectric portions arranged in the first trenches and covering lateral flanks of said region over the entire thickness of the second layer and a first part of the thickness of the first layer; first electrically conductive portions arranged in the first trenches and covering the lateral flanks of said region over a second part of the thickness of the first layer, and forming first electrodes of the diodes of said region; at least one second trench partially passing through the first layer and separating the portions of the first layer from the diodes of said region.

A light emitting device including a substrate, a first conductivity-type semiconductor layer, a mesa including a second conductivity-type semiconductor layer and an active layer, first and second contact electrodes respectively contacting the first and second conductivity-type semiconductor layers, a passivation layer covering the first and second contact electrodes, the mesa, and including first and second openings, and first and second bump electrodes electrically connected to the first and second contact electrodes through the first and second openings, respectively, in which the first and second bump electrodes are disposed on the mesa, the passivation layer is disposed between the first bump electrode and the second contact electrode, the first contact electrode includes a reflective material, and a portion of the first opening is surrounded with a side surface of the mesa, and another portion of the first opening is not surrounded with the side surface of the mesa.

A light emitting device for a display including a first LED stack configured to generate light having a first peak wavelength, a second LED stack disposed under the first LED stack, and configured to generate light having a second peak wavelength, a third LED stack disposed under the second LED stack, and configured to generate light having a third peak wavelength; and a floating reflection layer disposed over the first LED stack, in which the first peak wavelength is longer than the second and third peak wavelengths, the first LED stack has a roughened surface to increase the luminous intensity of the light generated in the first LED stack entering the second LED stack, and the floating reflection layer has a high reflectance of 80% or more over light having the first peak wavelength.

A display device according to one embodiment of the present disclosure may include a substrate including a plurality of concave portions, light emitting elements disposed at the plurality of concave portions, a first insulating layer disposed on the substrate and the light emitting element, a transistor disposed on the first insulating layer and including an active electrode and a gate electrode, a first hole included in the active electrode, a second hole included in the first insulating layer, and a connection electrode disposed in the first hole and the second hole, wherein the light emitting element may be electrically connected to the active electrode by the connection electrode.

Light-emitting diodes (LEDs), and more particularly edge structures for light shaping in LED chips are disclosed. Edge structures may include a repeating pattern of features that is formed along one or more mesa sidewalls of active LED structure mesas. Such active LED structure mesas may include a p-type layer, an active layer, and at least a portion of an n-type layer. Features of the repeating pattern may be configured with a size and/or shape to promote redirection of laterally propagating light from the active layer at the mesa sidewalls. In this manner, light that may otherwise escape the LED chip at the mesa sidewalls may be redirected toward an intended emission direction for the LED chip. Certain aspects include reflective structures that are provided on the active LED structures mesas and are further arranged to extend past the active LED structure mesas to cover the repeating pattern of features.

The present disclosure relates to an epitaxial wafer and a preparing method thereof, and a light-emitting device. The epitaxial wafer includes a substrate and an epitaxial stack, the epitaxial stack is disposed on the substrate, and the epitaxial stack includes a first epitaxial structure, a conductive adhesive layer, and a second epitaxial structure which are sequentially stacked in a direction parallel to an extension direction of the substrate. The first epitaxial structure is adhesively fixed to the second epitaxial structure through the conductive adhesive layer. The first epitaxial structure includes a first N-type semiconductor layer, a first active layer, and a first P-type semiconductor layer. The second epitaxial structure includes a second N-type semiconductor layer, a second active layer, and a second P-type semiconductor layer.