Patent classifications
H01L33/40
RADIATION-EMITTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING A RADIATION-EMITTING SEMICONDUCTOR CHIP
A radiation-emitting semiconductor chip may include a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer, a first metallic mirror with which charge carriers can be embedded into the first semiconductor layer, a first metallic contact layer disposed atop the first metallic mirror, and a second metallic contact layer disposed atop the first metallic contact layer. A first seed layer may be disposed between the first metallic contact layer and the first metallic mirror. A second seed layer may be disposed between the first metallic contact layer and the second metallic contact layer. The radiation-emitting semiconductor chip may include a radiation exit face having a multitude of emission regions. The first metallic mirror may have a multitude of cutouts that each define a lateral extent of one of the emission regions.
SEMICONDUCTOR LIGHT EMITTING DEVICE
A semiconductor light emitting device including a substrate; a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially stacked on the substrate; a transparent electrode layer on the second conductivity-type semiconductor layer; a first insulating layer on the transparent electrode layer and having a plurality of first through-holes; a multilayer insulating structure on the first insulating layer and having a plurality of second through-holes overlapping the plurality of first through-holes, respectively, the multilayer insulating structure being spaced apart from an edge of the light emitting structure; a reflective electrode layer on the multilayer insulating structure and connected to the transparent electrode layer through the plurality of first through-holes and the plurality of second through-holes; and a second insulating layer between the multilayer insulating structure and the reflective electrode layer.
DISPLAY DEVICE
A display device according to one embodiment of the present disclosure may include a substrate including a plurality of concave portions, light emitting elements disposed at the plurality of concave portions, a first insulating layer disposed on the substrate and the light emitting element, a transistor disposed on the first insulating layer and including an active electrode and a gate electrode, a first hole included in the active electrode, a second hole included in the first insulating layer, and a connection electrode disposed in the first hole and the second hole, wherein the light emitting element may be electrically connected to the active electrode by the connection electrode.
DISPLAY DEVICE
A display device according to one embodiment of the present disclosure may include a substrate including a plurality of concave portions, light emitting elements disposed at the plurality of concave portions, a first insulating layer disposed on the substrate and the light emitting element, a transistor disposed on the first insulating layer and including an active electrode and a gate electrode, a first hole included in the active electrode, a second hole included in the first insulating layer, and a connection electrode disposed in the first hole and the second hole, wherein the light emitting element may be electrically connected to the active electrode by the connection electrode.
EDGE STRUCTURES FOR LIGHT SHAPING IN LIGHT-EMITTING DIODE CHIPS
Light-emitting diodes (LEDs), and more particularly edge structures for light shaping in LED chips are disclosed. Edge structures may include a repeating pattern of features that is formed along one or more mesa sidewalls of active LED structure mesas. Such active LED structure mesas may include a p-type layer, an active layer, and at least a portion of an n-type layer. Features of the repeating pattern may be configured with a size and/or shape to promote redirection of laterally propagating light from the active layer at the mesa sidewalls. In this manner, light that may otherwise escape the LED chip at the mesa sidewalls may be redirected toward an intended emission direction for the LED chip. Certain aspects include reflective structures that are provided on the active LED structures mesas and are further arranged to extend past the active LED structure mesas to cover the repeating pattern of features.
DISPLAY APPARATUS
A display apparatus includes a circuit substrate with driving circuits and first bonding electrodes, and a pixel array having LED cells, each of the LED cells including first and second conductivity-type semiconductor layers with an active layer therebetween, second bonding electrodes on the first bonding electrodes, wavelength converters on the LED cells, an upper semiconductor layer on the LED cells and having a partition structure surrounding side snakes of the wavelength converters and separating the wavelength converters, a first reflective electrode on the side surfaces of the LED cells, spaced from the LED cells by a passivation layer, and extending between the LED cells, second reflective electrodes on the lower surfaces of the LED cells and connected to the second conductivity-type semiconductor layers, a common electrode on at least one side of the LED cells, and a pad electrode outside the LED cells and electrically connected to the driving circuits.
Chip-scale package light emitting diode
A chip-scale package type light emitting diode includes a first conductivity type semiconductor layer, a mesa, a second conductivity type semiconductor layer, a transparent conductive oxide layer, a dielectric layer, a lower insulation layer, a first pad metal layer, and a second pad metal layer, an upper insulation layer. The upper insulation layer covers the first pad metal layer and the second pad metal layer, and includes a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings of the dielectric layer include openings that have different sizes from one another.
MICRO LIGHT EMITTING DIODE CHIP
A micro light emitting diode chip including a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a first-type electrode, and a second-type electrode is provided. The first-type semiconductor layer has a first high-concentration doping region and a first low-concentration doping region. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first-type electrode is directly contacted and electrically connected to the first high-concentration doping region. The second-type electrode is electrically connected to the second-type semiconductor layer.
SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor stack, a third semiconductor structure, a dielectric layer, and a reflective layer under the third semiconductor structure. The semiconductor stack includes a first semiconductor structure, an active structure, a second semiconductor structure. The first semiconductor structure has a first surface which includes a first portion and a second portion, and the first surface has a first area. The third semiconductor structure connects to the first portion, and has a second surface with a second area. The dielectric layer connects to the second portion and includes a plurality of openings, and the plurality of openings have a third area. A ratio of the second area to the first area is between 0.1˜0.7, and a ratio of the third area to the first area is less than 0.2.
Tuning of emission properties of quantum emission devices using strain-tuned piezoelectric template layers
A quantum device includes a substrate including a first material and including an upper surface thereof, a first layer comprising a compound of the first material disposed on the upper surface of the substrate, a second layer, comprising a metal oxide, disposed on the first layer, a third layer, comprising a noble metal, disposed on the second layer, a fourth layer, comprising a metal oxide, disposed on the third layer, a fifth layer, comprising a piezoelectric material, disposed on the fourth layer, a sixth layer, comprising a noble metal, disposed on the fifth layer, a seventh layer, comprising a material capable of quantum emission, disposed on the sixth layer, and an eighth layer, comprising a noble metal, disposed on the seventh layer, and at least one of the eighth layer and the seventh layer are sized to enable quantum emission from the seventh layer.