H01L39/02

INTERCONNECT STRUCTURES FOR ASSEMBLY OF SEMICONDUCTOR STRUCTURES INCLUDING SUPERCONDUCTING INTEGRATED CIRCUITS

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Josephson Junction using Molecular Beam Epitaxy
20180013053 · 2018-01-11 ·

According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

Qubit and Coupler Circuit Structures and Coupling Techniques

Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).

PARAMETRIC AMPLIFIER AND USES THEREOF

A parametric amplifier for amplifying an input signal includes a resonator comprising a Josephson junction. The Josephson junction comprises a first superconductor component, a second superconductor component and a semiconductor component. The semiconductor component is configured to enable coupling of the first and second superconductor components. The parametric amplifier further comprises a gate electrode configured to apply an electrostatic field to the semiconductor component of the Josephson junction for tuning the parametric amplifier. Such parametric amplifiers are useful for amplifying signals in the microwave frequency range. Tuning the junction by electrostatic gating may allow for improved scalability compared to tuning using magnetic flux. Also provided are the use of the parametric amplifier to amplify a signal; and a method of amplifying a signal.

Low footprint resonator in flip chip geometry
11527696 · 2022-12-13 · ·

A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.

Vertical AL/EPI SI/AL, and also AL/AL oxide/AL, josephson junction devices for qubits

A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction.

INTEGRATION SCHEME FOR SHUNTED JOSEPHSON JUNCTIONS

Materials with etch selectivity with respect to one another and one or more additional etch-stop layers are used in a Josephson junction structure to allow for integration with a Josephson junction with supporting structures such as resistors. Selective etch processes compatible with high volume manufacturing are used to pattern various layers of the Josephson junction structure to provide a Josephson junction, which is electrically coupled to a support structure.

SUPERCONDUCTOR COMPOSITES AND DEVICES COMPRISING SAME
20220376162 · 2022-11-24 ·

Compositions comprising a) one or more amorphous superconductor layers bound to one or more flexible substrate layers, or b) one or more superconductor layers bound to one or more layers of a high dielectric material are disclosed. Furthermore, provided herein are articles comprising one or more compositions of the invention and method of manufacturing thereof.

HIGH TEMPERATURE SUPERCONDUCTOR-BASED INTERCONNECT SYSTEMS WITH A LOWERED THERMAL LOAD FOR INTERCONNECTING CRYOGENIC ELECTRONICS WITH NON-CRYOGENIC ELECTRONICS

High temperature superconductor (HTS)-based interconnect systems comprising a cable including HTS-based interconnects are described. Each of the HTS-based interconnects includes a first portion extending from a first end towards an intermediate portion and a second portion extending from the intermediate portion to a second end. Each of the HTS-based interconnects includes a substrate layer formed in the first portion, in the intermediate portion, and in the second portion, a high temperature superconductor layer formed in at least a sub-portion of the first portion, in the intermediate portion, and in the second portion, and a metallic layer formed in the first portion and in at least a sub-portion of the intermediate portion. The HTS-based interconnect system includes a thermal load management system configured to maintain the intermediate portion of each of the HTS-based interconnects at a predetermined temperature in a range between a temperature of 60 kelvin and 92 kelvin.

ELECTRONIC CIRCUIT, CALCULATION DEVICE, AND METHOD FOR MANUFACTURING THE ELECTRONIC CIRCUIT
20220376161 · 2022-11-24 · ·

According to one embodiment, an electronic circuit includes a first nonlinear element, a second nonlinear element, and a third nonlinear element. The first nonlinear element includes a first element Josephson junction provided in a first region of a first surface including the first region and a second region. The second nonlinear element includes a second element Josephson junction provided in the second region. The third nonlinear element includes a Josephson junction circuit. At least a part of the Josephson junction circuit is provided on a second surface. The second surface is separated from the first surface in a first direction crossing the first surface. The second surface is along the first surface. The third nonlinear element is configured to be coupled with the first nonlinear element. The third nonlinear element is configured to be coupled with the second nonlinear element.