H01L39/08

Impedance matched superconducting nanowire photodetector for single- and multi-photon detection

Conventional readout of a superconducting nanowire single-photon detector (SNSPD) sets an upper bound on the output voltage to be the product of the bias current and the load impedance, I.sub.B×Z.sub.load, where Z.sub.load is limited to 50Ω in standard RF electronics. This limit is broken/exceeded by interfacing the 50Ω load and the SNSPD using an integrated superconducting transmission line taper. The taper is a transformer that effectively loads the SNSPD with high impedance without latching. The taper increases the amplitude of the detector output while preserving the fast rising edge. Using a taper with a starting width of 500 nm, a 3.6× higher pulse amplitude, 3.7× faster slew rate, and 25.1 ps smaller timing jitter was observed. The taper also makes the detector's output voltage sensitive to the number of photon-induced hotspots and enables photon number resolution.

Diode devices based on superconductivity
11502237 · 2022-11-15 · ·

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

Reinforced thin-film semiconductor device and methods of making same
11469300 · 2022-10-11 · ·

A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.

Superconductive Memory Cells and Devices
20220059160 · 2022-02-24 ·

An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.

METHODS AND STRUCTURE TO PROBE THE METAL-METAL INTERFACE FOR SUPERCONDUCTING CIRCUITS

A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.

Diode Devices Based on Superconductivity
20210408356 · 2021-12-30 ·

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

METHOD FOR THE IN SITU PRODUCTION OF MAJORANA MATERIAL SUPERCONDUCTOR HYBRID NETWORKS AND TO A HYBRID STRUCTURE WHICH IS PRODUCED USING THE METHOD

A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

METHOD FOR PROCESSING A SEMICONDUCTOR DEVICE WITH TWO CLOSELY SPACED GATES
20210391526 · 2021-12-16 ·

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

Superconducting stress-engineered micro-fabricated springs

A structure has a substrate, and a spring structure disposed on the substrate, the spring structure having an anchor portion disposed on the substrate, an elastic material having an intrinsic stress profile that biases a region of the elastic material to curl away from the substrate, and a superconductor film in electrical contact with a portion of the elastic material. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising at least an elastic material, releasing a portion of the elastic material so that portion lifts out of a plane of the substrate to form elastic springs, and coating the elastic springs with a superconductor film.

REDUCING PARASITIC CAPACITANCE AND COUPLING TO INDUCTIVE COUPLER MODES
20210384402 · 2021-12-09 ·

A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.