Example embodiments relate to substrate integrated waveguide (SIW) transitions. An example SIW may include a dielectric substrate having a top surface and a bottom surface and a first metallic layer portion coupled to the top surface of the dielectric substrate that includes a single-ended termination, an impedance transformer, and a metallic rectangular patch located within an open portion in the first metallic layer portion such that the open portion forms a non-conductive loop around the metallic rectangular patch. The SIW also includes a second metallic layer portion coupled to the bottom surface of the dielectric substrate and metallic via-holes electrically coupling the first metallic layer to the second metallic layer. The SIW may be implemented in a radar unit to couple antennas to a printed circuit board (PCB). In some examples, the SIW may be implemented with only a non-conductive opening that lacks the metallic rectangular patch.

Aspects of the present disclosure are directed to a photonic integrated circuit (PIC) having a resistivity-engineered substrate to suppress radio-frequency (RF) common-mode signals. In some embodiments, a semiconductor substrate is provided that comprises two portions having different levels of resistivity to provide both suppression of common mode signals, and reduction of RF absorption loss for non-common mode RF signals. In such embodiments, a bottom portion of the semiconductor substrate has a low resistivity to suppress common mode via RF absorption, while a top portion of the semiconductor substrate that is adjacent to conductors in the IC has a high resistivity to reduce RF loss.

An antennas-in-package (AiP) verification board is provided, which includes a carrier board configured for disposing an antenna array or an electronic circuit; and a plurality of SMPM connectors. The plurality of SMPM connectors are arranged in an array on the carrier board and electrically connected with the antenna array or the electronic circuit of the carrier board for testing the characteristics of the antenna array on the carrier board or the characteristics of the electronic circuit on the carrier board. The AiP verification board is fixed on a beamforming test platform. In addition to the aforementioned AiP verification board, an AiP verification board including a plurality of adaptor structures and an AiP verification board including a plurality of connectors and a plurality of adaptor structures are also provided.

A downhole energy transmission system is described. The system can include a tubing string having a number of tubing pipe disposed within an annulus formed by a casing string disposed within a wellbore, where the tubing string has at least one wall forming a cavity. The system can also include a remote electrical device disposed within the cavity of the tubing string at a first location. The system can further include a first stripline cable disposed on an outer surface of the tubing string, where the first stripline cable transmits a first electromagnetic directional traveling wave received from an energy source. The system can also include a second stripline cable disposed adjacent to the first stripline cable at the first location, where the second stripline cable is electrically coupled to the remote electrical device.

A planar antenna includes a dielectric layer including a first surface and a second surface on a side opposite from the first surface, an antenna conductor provided on the first surface, a ground conductor provided on the first surface or the second surface, or provided on both of the first surface and the second surface, and a transmission line including a signal line that is connected to the antenna conductor or provided in proximity to the antenna conductor, wherein a dielectric portion of the dielectric layer that is in contact with the signal line has a loss tangent of 0.007 or less at 28 GHz.

A semiconductor device includes a first transmission line and a second transmission line. The semiconductor device further includes a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material surrounds the second transmission line. The semiconductor device further includes a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material is separated from the first transmission line and the second transmission line.

A transmission line design includes a first transmission line configured to transfer at least one first signal. The transmission line design further includes a second transmission line configured to transfer at least one second signal, wherein the second transmission line is spaced from the first transmission line. The transmission line design further includes a high-k dielectric material between the first transmission line and the second transmission line. The transmission line design further includes a dielectric material surrounding the high-k dielectric material, the first transmission line and the second transmission line, wherein the dielectric material is different from the high-k dielectric material.

A compact impedance transformer is disclosed having a first dielectric substrate, a first planar conductor disposed on a top surface of the first dielectric substrate in a loop, a second planar conductor disposed on a bottom surface of the first dielectric substrate in a second loop, wherein the first planar conductor and the second planar conductor are substantially identical and in stacked alignment. A second dielectric substrate has a third planar conductor disposed on a top surface of the second dielectric substrate in a third loop, and a fourth planar conductor disposed on a bottom surface of the second dielectric substrate in a fourth loop, wherein the third planar conductor and the fourth planar conductor are substantially identical and in stacked alignment. An interconnect structure between terminals of the first planar conductor, the second planar conductor, the third planar conductor, and the fourth planar conductor provide impedance transformations.

Aspects of the present disclosure are directed to a photonic integrated circuit (PIC) having a resistivity-engineered substrate to suppress radio-frequency (RF) common-mode signals. In some embodiments, a semiconductor substrate is provided that comprises two portions having different levels of resistivity to provide both suppression of common mode signals, and reduction of RF absorption loss for non-common mode RF signals. In such embodiments, a bottom portion of the semiconductor substrate has a low resistivity to suppress common mode via RF absorption, while a top portion of the semiconductor substrate that is adjacent to conductors in the IC has a high resistivity to reduce RF loss.

A transmission line device includes a first multilayer substrate with a transmission line including laminated insulating base materials and a conductor pattern on the insulating base materials, and a second multilayer substrate defining a connected member to which the transmission line of the first multilayer substrate is connected. The conductor pattern includes a signal conductor pattern and a signal electrode pad electrically connected to the signal conductor pattern. The first multilayer substrate includes a resist film provided on a surface of a laminate of the insulating base materials, and the resist film includes an opening that is separated from an outer edge of the signal electrode pad in a surface direction of the laminate of the insulating base material and exposes the signal electrode pad.