Provided is a novel multi-level inverter with mixed device types and methods of controlling same. This novel multi-level inverter topology and control method allows the use of high frequency switching devices for controlled PWM switching, while also using lower frequency switching devices for directional switches. This combination of high frequency PWM switching devices with low frequency directional switching devices allows a cost reduction without a significant performance degradation.

A low EMI driver apparatus includes: a driver circuit configured to generate a driving signal according to a switch control signal, so as to drive at least one switch; and a driving strength control circuit configured to randomly control a driving strength of the driver circuit, thereby reducing an EMI generated when the at least one switch is driven according to the driving signal. In a specific form of the low EMI driver apparatus, the at least one switch includes plural switches, and the low EMI driver apparatus further includes: a dead time control circuit configured to randomly control a dead time between ON times of the plural switches, so as to reduce the EMI generated when the switches are driven according to the driving signal.

Embodiments of the present application disclose a multi-level inverter clamping modulation method and apparatus, and an inverter. Switching elements of an inverter are controlled when an output voltage of the inverter crosses zero, and switching elements in each inverter bridge arm of an active clamp multi-level inverter include an internal tube, an external tube, and a clamping tube. The internal tube and the external tube are connected in series between a positive bus and a negative bus, the clamping tube is connected between a common terminal of the internal tube and the external tube and a bus, the internal tube is a low-frequency switching element, and the external tube and the clamping tube are high-frequency switching elements.

A switching controller generates control pulses for specifying on/off states of a first transistor and a second transistor. One end of a capacitor is coupled to a switching node. A constant voltage is applied to the other end of the capacitor via a rectifier element. A dead time controller controls a delay time between adjacent edges of the first control pulse and the second control pulse according to a sensing voltage across both ends of the capacitor.

An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.

A method for operating a multi-level bridge power converter includes providing a plurality of switching devices of the power converter in one of a neutral point clamped topology or an active neutral point clamped topology. The method also includes providing a plurality of deadtimes for the switching devices. Further, the method includes selecting one of the deadtimes for each of the switching devices such that at least two of the switching devices operate according to different deadtimes. Moreover, the method includes operating the switching devices at the selected deadtimes to allow a first group of the switching devices to switch slower than a second group of the switching devices such that the first group of the switching devices satisfy safe operating requirements while the second group of the switching devices switch faster than the first group.

The invention relates to a method for determining an error voltage of a current converter to which a load, in particular in the form of a three-phase machine such as an asynchronous machine, is connected, is determined and if necessary compensated, wherein an output voltage on the current converter is increased stage-by-stage or step-by-step and which is measured here as a current adjusting a step response. The invention further relates to a three-phase machine, for example in the form of an asynchronous machine having power electronics comprising a current converter and in the form of a compensation device for compensating the error voltage of the current converter. The invention further relates to a method for operating and/or controlling such a three-phase machine, in which the error voltage of the current converter is determined and compensated. According to the invention, the error voltage is determined from the current measured as a step response and from a resistance of the load, wherein said resistance is determined from a target voltage jump and from a simultaneously measured actual current jump in a relatively high current range of at least 30% of at least 50% of the rated current of the end stage of the current converter.

A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

A gate drive circuit in a switching circuit including a switching terminal connected to a node that is connected to a high-side transistor and a low-side transistor, and connected to an end of a boot-strap capacitor, a bootstrap terminal connected to another end of the bootstrap capacitor, a high-side driver having an output terminal connected to a gate of the high-side transistor, an upper power supply node connected to the bootstrap terminal, and a lower power supply node connected to the switching terminal, a low-side driver having an output terminal connected to a gate of the low-side transistor, a rectifying device for applying a constant voltage to the bootstrap terminal, and a dead time controller for controlling a length of a dead time during which the high-side transistor and the low-side transistor are simultaneously turned off, based on a potential difference between the bootstrap terminal and the switching terminal.

A power system includes a pulse width modulation device. The pulse width modulation device outputs first, second, third and fourth driving signals. The pulse width modulation device receives a control signal. The control signal is divided into a positive periodic signal and a negative periodic signal. A portion of the positive periodic signal higher than or equal to a maximum threshold voltage is clamped as the maximum threshold voltage to generate a first comparison waveform. The positive periodic signal is clamped as the reference voltage level to generate a second comparison waveform. According to the first comparison waveform, a first ramp signal is generated. According to the second comparison waveform, a first pulse width modulation signal is generated. The first, second, third and fourth driving signals are adjusted according to the first ramp signal and the first pulse width modulation signal.