In an embodiment a circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.

An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.