An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (V.sub.buf) for a first pulse period to charge the resonator only partially towards the input voltage (V.sub.buf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).

A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

VLSI distributed LC resonant clock networks having reduced inductor dimensions as well as simplified decoupling capacitances that are obtained by including one or more compensation capacitors. A compensation capacitor can be added in parallel with a clock capacitance and/or in parallel with a clock inductor. The presence of a compensation capacitance reduces the overhead associated with the inductor and the decoupling capacitor. The compensation capacitor (s) can be selectively switched into the network to create scalable resonant frequencies.

A drive-mode oscillator module for use within a micro-electro-mechanical system (MEMS) device is described. The drive-mode oscillator module is arranged to receive a proof-mass measurement signal from a proof-mass of the MEMS device and to output a proof-mass actuation signal to the proof-mass of the MEMS device. The drive-mode oscillator module comprises a first, higher gain accuracy drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during an active mode of the MEMS device, and a second, lower power consumption drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during a standby mode of the MEMS device.

An oscillator circuit has a reconfigurable oscillator amplifier. The reconfigurable oscillator amplifier is used to be coupled to a resonant circuit in parallel. The reconfigurable oscillator amplifier supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier employs one of the different circuit configurations under one of the different operation modes.

A crystal oscillator circuit is provided. The crystal oscillator circuit includes an oscillator start-up circuit having a first output terminal and a second output terminal, where the second output terminal outputs a first oscillation signal; and a waveform conversion circuit configured to convert the first oscillation signal to a rectangular wave signal. The crystal oscillator circuit also includes a first current source configured to output a first current to drive the oscillator start-up circuit; and a second current source configured to output a second current, and being connected in parallel with the first current source to jointly drive the oscillator start-up circuit. Further the crystal oscillator circuit includes a pulse generation circuit configured to generate a control pulse signal to control the second current source to output the second current after power on and to stop outputting the second current after a preset time.