Cross-coupled structures are provided. Cross-coupled structures may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor, the second transistor, and the fourth transistor may be spaced apart from each other in a first direction, and the third transistor and the second transistor may be stacked in a second direction that is perpendicular to the first direction. The third transistor and the second transistor may include a common gate structure, a first portion of the common gate structure may be a gate structure of the second transistor, and a second portion of the common gate structure may be a gate structure of the third transistor.

A signal generator includes a first voltage generator, a second voltage generator, an operational amplifier, and an oscillator. The first voltage generator generates a first voltage, and the second voltage generator generates a second voltage. The operational amplifier generates an amplified error signal based on the first voltage and the second voltage, and the oscillator generates a periodic signal based on the amplified error signal. The first voltage generator and the second voltage generator are configured to generate their respective voltages based on the periodic signal. As a result, frequency deviation in the periodic signal may be corrected, for example, without increasing the source current of the oscillator or the gain of the operational amplifier. Also, improved phase noise performance may also be achieved through an increase in loop gain.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

A switchable element, a device and a method for analogue and programmable computing operating on electromagnetic waves having a frequency, wherein the switchable element is configured to configured to, in response to an activation signal, switch from having a first dielectric permittivity for electromagnetic waves having a frequency to having a second dielectric permittivity for electromagnetic waves having the frequency, and the device comprises a plurality of the switchable elements that are adapted to be switched individually in accordance with the computing operation.

An information handling system includes an intrusion detection circuit having two inductors and an amplifier circuit. The amplifier circuit is configured to identify an increase in inductive coupling between the inductors in response to a change in position of a cover.

A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

There is provided a power supply device configured to boost an input voltage to output an output voltage, the power supply device including: an oscillator circuit configured to receive the input voltage and to output an oscillation signal; a step-up circuit configured to output a boost voltage based on the oscillation signal; a first hysteresis comparator and a second hysteresis comparator configured to compare boost voltages with threshold values; a first switch that is connected between the oscillator circuit and the step-up circuit and that is controlled based on a comparison result of the first hysteresis comparator; and a second switch that is connected to an output terminal configured to output the output voltage and that is controlled based on a comparison result of the second hysteresis comparator.

A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.

An integrated circuit includes an oscillator and a power amplifier. The oscillator includes a first node, a second node, and a network of one or more reactive components coupled between the first node and the second node. The power amplifier includes a first input coupled to the first output of the oscillator, a second input coupled to the second output of the oscillator, and an output. The power amplifier includes a coarse gain control circuit, a first amplifier stage, and a second amplifier stage.