An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal. The embodiment of the present disclosure eliminates the need to provide an additional common mode feedback generation circuit, and does not require an increase in power consumption, achieving the advantages of smaller occupied area, lower power consumption, less noise, and better performance as compared with a relaxation oscillator of the related art.

The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal. The embodiment of the present disclosure eliminates the need to provide an additional common mode feedback generation circuit, and does not require an increase in power consumption, achieving the advantages of smaller occupied area, lower power consumption, less noise, and better performance as compared with a relaxation oscillator of the related art.

An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.

An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.

A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2.sup.k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2.sup.k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal. The embodiment of the present disclosure eliminates the need to provide an additional common mode feedback generation circuit, and does not require an increase in power consumption, achieving the advantages of smaller occupied area, lower power consumption, less noise, and better performance as compared with a relaxation oscillator of the related art.

The present disclosure relates to a relaxation oscillator, an integrated circuit and an electronic apparatus, the relaxation oscillator comprising a first signal generation module and an oscillation module configured to output a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal being opposite in phase, the oscillation module comprising a first switch, a second switch, a capacitor, and a comparison unit. The oscillation module according to the disclosed embodiment using a floating amplifier to implement a comparator, where in a pre-charging stage, the first switch and the second switch are turned on to charge the capacitor, and a common mode of the first oscillation signal and the second oscillation signal is determined; in a comparing stage, the first switch and the second switch are turned off to output the oscillation signal. The embodiment of the present disclosure eliminates the need to provide an additional common mode feedback generation circuit, and does not require an increase in power consumption, achieving the advantages of smaller occupied area, lower power consumption, less noise, and better performance as compared with a relaxation oscillator of the related art.