A crystal oscillator is coupled to a digital automatic gain control (AGC) having oscillation detection and amplitude control loops. The oscillation detection loop may increase the transconductance (gm) of the oscillator transistor until oscillation is detected therefrom. Then the amplitude control loop detects the amplitudes of oscillations from the crystal oscillator, compares these amplitudes to high and low voltage references and generates digital signals to find a critical transconductance (gm) for an oscillator amplifier and control this gm to maintain a constant oscillation waveform amplitude therefrom. An up/down counter defines the servo control loop bandwidth/update-rate according to an update clock rate thereto. Loop stability is achieved when the control loop bandwidth is less than the start-up time required for the oscillation envelope of the crystal oscillator to grow for oscillation. An oscillator failure detector may also be provided.

An oscillator circuit includes: a first temperature detector, detecting an internal temperature of the oscillator circuit; a current generator, generating a heater current so that the internal temperature matches a target temperature; a first and second heater, heating the resonator and the integrated circuit, respectively, based on the heater current; a second temperature detector, detecting a temperature of the integrated circuit; a first compensation voltage generation circuit, generating a first compensation voltage for compensating for a frequency variation due to a temperature change in the integrated circuit, based on a detection result of the second temperature detector; a second compensation voltage generation circuit, generating a second compensation voltage for compensating for a frequency variation due to a temperature change in the resonator, based on a detection result of the first temperature detector; and an oscillator, generating an oscillation signal based on the first and second compensation voltages.

A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

A vibration device includes a semiconductor substrate having a first surface and a second surface in an obverse-reverse relationship, a vibration element disposed on the first surface, a lid bonded to the first surface, an integrated circuit disposed on the first surface, a terminal disposed on the second surface, a through electrode which penetrates the semiconductor substrate, and is configured to electrically couple the terminal and the integrated circuit to each other, and a first capacitor which is provided with a first recess provided to the semiconductor substrate and opening in the first surface, an insulating film disposed on an inside surface of the first recess, and an electrically-conductive material filling the first recess, and has a first capacitance between the electrically-conductive material and the semiconductor substrate, wherein the electrically-conductive material does not have contact with the terminal at the second surface side.

A circuit device includes an oscillation circuit configured to generate an oscillation signal, a first pre-driver disposed in a posterior stage of the oscillation circuit, a first output driver disposed in a posterior stage of the first pre-driver, a first regulator configured to supply a first regulated voltage to the first pre-driver, and a second regulator configured to supply a second regulated voltage to the first output driver, wherein the second regulator is shorter in transient response time than the first regulator.

A resonator device includes: a base including a semiconductor substrate; a resonator element; and a lid to be bonded to the base, the lid and the base forming a cavity for accommodating the resonator element. An integrated circuit is disposed at the semiconductor substrate, the integrated circuit including an oscillation circuit electrically coupled to the resonator element, a memory circuit configured to store a reference value of an output characteristic of the resonator element, and a determination circuit configured to compare a detection value of the output characteristic of the resonator element with the reference value and determine an airtight state inside the cavity based on a comparison result.

A circuit device includes a first terminal to be coupled to one end of a resonator, a second terminal to be coupled to another end of the resonator, an amplifying element configured to amplify a signal from the first terminal to output the signal amplified to the second terminal, a first resistor element disposed on a signal path between an input node and an output node of the amplifying element, a capacitance element disposed on a signal path between the first terminal and the input node, and a first switch element configured to switch electrical coupling between the input node and a ground.

An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.

A circuit device includes an oscillation circuit configured to generate an oscillation signal, a first pre-driver disposed in a posterior stage of the oscillation circuit, a first output driver disposed in a posterior stage of the first pre-driver, a first regulator configured to supply a first regulated voltage to the first pre-driver, and a second regulator configured to supply a second regulated voltage to the first output driver, wherein the second regulator is shorter in transient response time than the first regulator.

A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.