H03D2200/0062

SIGNAL DOWN-CONVERSION

An apparatus (7) for down-converting a sampled signal comprises a processing system (206) configured to apply a mixing-and-combining operation repeatedly to successive sub-sequences of N input samples, X, representative of a signal and having an initial sampling rate, M, to generate a sequence of output samples, Y, having an output rate, T, lower than the initial sampling rate M. The sub-sequences of the N input samples, X, are spaced at intervals that correspond to the output rate M. The mixing-and-combining operation generates a respective output sample Y from each sub-sequence, where Y depends on a set of products of the input samples X of the sub-sequence with respective values derived from a periodic mixing signal having a mixing frequency.

Phase Sector Based Signal Charge Acquistion
20170222767 · 2017-08-03 · ·

A method and system for extracting values representative of modulation signal components from a modulated signal, the modulated signal containing a modulation signal, including developing a local clock signal which correlates in time to the modulated signal and includes a number of phase sectors per cycle and converting the modulated signal into a current that is representative of the signal and routing the current to the inverting input of an amplifier and charging one of a plurality of capacitive devices during each phase sector and sequentially connecting the capacitive devices between the output of the amplifier and the inverting input of the amplifier in non-overlapping sequences, the total of sequences being equal to one full cycle of the clock.

DIGITAL FREQUENCY CONVERTER AND METHOD OF PROCESSING IN A DIGITAL FREQUENCY CONVERTER
20170272035 · 2017-09-21 · ·

A frequency converter comprising a frequency transposition block for samples (11.sub.Q.sub._.sub.1, 11.sub.Q.sub._.sub.2), a filtering block (12.sub.Q.sub._.sub.1, 12.sub.Q.sub._.sub.2), the filtered samples y(n) verifying y(n)=c(0).Math.x(n)+c(1).Math.x(n−1)+c(2).Math.x(n−2)+ . . . +c(p−1).Math.x(n−p+1)+c(p).Math.x(n−p)+c(p−1).Math.x(n−p−1)+ . . . + . . . +c(1).Math.x(n−2.Math.p+1)+c(0).Math.x(n−2.Math.p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0).Math.x(n), c(1).Math.x(n−1), c(2).Math.x(n−2), . . . , c(p).Math.x(n−p) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p−1).Math.x(n−p−1), . . . , c(1).Math.x(n−2.Math.p+1), c(0).Math.x(n−2.Math.p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(n−m); and determining y(n) by summation of the first and second terms.

Signal down-conversion

An apparatus (7) for down-converting a sampled signal comprises a processing system (206) configured to apply a mixing-and-combining operation repeatedly to successive sub-sequences of N input samples, X, representative of a signal and having an initial sampling rate, M, to generate a sequence of output samples, Y, having an output rate, T, lower than the initial sampling rate M. The sub-sequences of the N input samples, X, are spaced at intervals that correspond to the output rate M. The mixing-and-combining operation generates a respective output sample Y from each sub-sequence, where Y depends on a set of products of the input samples X of the sub-sequence with respective values derived from a periodic mixing signal having a mixing frequency.

Digital frequency converter and method of processing in a digital frequency converter
10230331 · 2019-03-12 · ·

A frequency converter comprising a frequency transposition block for samples (11.sub.Q.sub._.sub.1, 11.sub.Q.sub._.sub.2), a filtering block (12.sub.Q.sub._.sub.1, 12.sub.Q.sub._.sub.2), the filtered samples y(n) verifying y(n)=c(0).Math.x(n)+c(1).Math.x(n1)+c(2).Math.x(n2)+ . . . +c(p1).Math.x(np+1)+c(p).Math.x(np)+c(p1).Math.x(np1)+ . . . + . . . +c(1).Math.x(n2.Math.p+1)+c(0).Math.x(n2.Math.p), wherein x( ) are the transposed samples and c(0), . . . c(p) are the real coefficients of the filter; and being adapted for, during a cycle for determining the value of the filtered sample y(n): calculating the first terms c(0).Math.x(n), c(1).Math.x(n1), c(2).Math.x(n2), . . . , c(p).Math.x(np) by multiplying the respective coefficients and transposed samples, and storing in memory said first calculated terms; reading the second terms c(p1).Math.x(np1), . . . , c(1).Math.x(n2.Math.p+1), c(0).Math.x(n2.Math.p), calculated and stored in memory during previous cycles for determining the value of filtered samples y(nm); and determining y(n) by summation of the first and second terms.

Real-time I/Q imbalance correction for wide-band RF receiver

A receiver apparatus models and corrects the frequency-dependent and the frequency-independent mismatches between I and Q paths jointly by polynomial estimations. The receiver apparatus may sample digitized I and Q path signals. The sampled data point may be modeled in equations with real and imaginary components. The sampled discrete time-domain data may be converted to frequency-domain data. Multiple statistics values based on the frequency-domain data may be computed. Coefficients for the polynomial equations may be estimated based on the computed statistic values. The channel mismatches may be estimated from the polynomial equations and used to compensate the mismatch either on the I path or the Q path.

Phase sector based signal charge acquisition
12250086 · 2025-03-11 ·

A method and system for extracting values representative of modulation signal components from a modulated signal, the modulated signal containing a modulation signal, including developing a local clock signal which correlates in time to the modulated signal and includes a number of phase sectors per cycle and converting the modulated signal into a current that is representative of the signal and routing the current to the inverting input of an amplifier and charging one of a plurality of capacitive devices during each phase sector and sequentially connecting the capacitive devices between the output of the amplifier and the inverting input of the amplifier in non-overlapping sequences, the total of sequences being equal to one full cycle of the clock.