A compensation circuit includes a power amplifier, a current bias circuit, a power detection circuit and a current control circuit; the power detection circuit is configured to detect the voltage amplitude of the radio frequency input signal of the power amplifier and output a reference current when the voltage amplitude meets a preset condition; the current control circuit is configured to receive a reference current and output a compensation current to the current bias circuit based on the reference current; the current bias circuit is configured to receive the compensation current and generate the direct-current bias current, and output the compensation current and the direct-current bias current to the power amplifier; and the power amplifier is configured to receive the compensation current and the direct-current bias current, and amplify the power of the radio frequency input signal based on the compensation current and the direct-current bias current.

An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

A surface acoustic wave device including a piezoelectric layer, an interdigital transducer electrode over the piezoelectric layer, and a polymeric roof layer arranged over the piezoelectric layer and interdigital transducer electrode. The polymeric roof layer is spaced apart from the piezoelectric layer to define a cavity to accommodate the interdigital transducer electrode. The polymeric roof layer is supported along a span of the polymeric roof layer by at least one pillar. The thermal conductivity of the pillar is greater than the thermal conductivity of the polymeric roof layer. Related wafer-level packages, radio frequency modules and wireless communication devices are also provided.

Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.

A power amplification circuit including: a power splitter which splits an input signal into a first signal and a second signal; a first carrier amplifier which amplifies the first signal to output a first amplified signal; a first peak amplifier which amplifies the second signal when a power level of the second signal is larger than or equal to a predetermined power level to output a second amplified signal; and a combiner which combines the first amplified signal and the second amplified signal, in which the first carrier amplifier and the first peak amplifier are provided to a same semiconductor substrate.

A circuit configured to amplify a signal from which an offset is cancelled includes an amplifier including an input stage configured to receive an input signal, the amplifier configured to amplify the input signal and output the amplified signal, and a switch including a transistor configured to reset the amplifier in response to a reset signal, the transistor including a body node connecting the transistor to the circuit, the transistor being configured to form a current path between the body node of the transistor and the input stage of the amplifier.

The present invention is in the field of booster stage circuit for a power amplifier, and an external supply voltage power amplifier comprising said booster stage circuit, such as for amplifying an electronic signal to a speaker system. These amplifiers may be provided with an external supply voltage.

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

The present disclosure relates to an amplifying circuit and a voltage generating circuit. The amplifying circuit includes: an operational amplifier, including a first input terminal, a second input terminal and an output terminal, and configured to be capable of outputting an output voltage corresponding to an input voltage from the output terminal to the first input terminal; a voltage dividing circuit, including a series circuit of a plurality of voltage dividing resistors disposed between the output terminal and a predetermined potential terminal, wherein the series circuit includes a feedback node connected to the second input terminal and a correction node different from the feedback node; and a correction circuit, including a diode inserted between the correction node and the predetermined potential terminal.

The present disclosure discloses a sample and hold amplifier circuit that includes a positive and a negative terminal capacitor arrays, a positive and a negative terminal switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal. In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a holding time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.