A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.

An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.

A clamp circuit comprises a first diode stack comprising one or more diodes and an array comprising a second diode stack comprising one or more diodes and a comparator configured to compare a first voltage at the first diode stack to a second voltage at the second diode stack.

A wireless communication device includes a signal generator supply a signal to an input node to which a power amplifier is connected. The power amplifier includes an inverter including a first transistor with a gate connected to the input node via a first signal path and a second transistor with a gate electrode connected to the input node via a second signal path. An output signal corresponding to the signal supplied to the input node is supplied from an output node between the first and second transistors. A filter is connected to the output node and outputs a filtered signal having a high frequency component removed. A bias application unit applies a first bias voltage to the first signal path and a second bias voltage to the second signal path. Levels of the bias voltages being set according to a direct current component in the filtered signal.

A power amplification system includes a Doherty power amplifier (PA) configured to receive a voltage supply signal and a radio-frequency (RF) signal and generate an amplified RF signal using the voltage supply signal, the Doherty PA including a carrier amplifier and a peaking amplifier. A carrier amplifier bias circuit and a peaking amplifier bias circuit coupled to one or more of the carrier amplifier and the carrier amplifier bias circuit over a coupling path are provided wherein the peaking amplifier bias circuit is configured to provide a peaking bias signal to the peaking amplifier based on a saturation level of the carrier amplifier.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to an absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a part of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for producing a reference current from the first and second correction currents and the gain current. The temperature correction circuit further includes an output for providing the reference current to the transistor.

A power amplifier apparatus is provided. The power amplifier apparatus includes a number of multi-stage power amplifiers and a bias circuit configured to generate a number of bias signals (e.g., bias current or bias voltage) to control (e.g., activate or deactivate) the multi-stage power amplifiers. In examples disclosed herein, only one of the multi-stage power amplifiers is activated at a given time. In this regard, the bias circuit can generate the bias signals to collectively activate one of the multi-stage power amplifiers, while deactivating the rest of the multi-stage power amplifiers. As such, it may be possible to control a larger number of power amplifier stages based on a smaller number of bias signals. As a result, it may be possible to eliminate a biasing bump pad(s) from the power amplifier apparatus, thus helping to reduce the footprint and cost of the power amplifier apparatus.

A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.