A differential tuned inductor and a multilayer tunable transformer for an integrated circuit device for microwave and RF applications are disclosed. The tunable inductor can be used in differential artificial delay lines to achieve delay tuning while preserving impedance matching. The tunable transformer can also be used for mixer drives to achieve wider operational performance.

An optical receiver disclosed includes a bias terminal, an input terminal, a photodiode, an amplifier circuit, a first resistor, a bypass circuit, a filter circuit, and a control circuit. The photodiode receives a bias from the filter circuit through the bias terminal, and outputs a current signal to the amplifier circuit through the input terminal. The amplifier circuit converts an input current to an output voltage. The bypass circuit electrically connected to the input terminal decreases a first input impedance viewed from the input terminal, when activated, and increases the first input impedance, when deactivated. The filter circuit increases a second input impedance viewed from the bias terminal, when a dumping function thereof is activated, and decreases the second input impedance, when the dumping function is deactivated. The control circuit activates the dumping function and the bypass circuit, when the output voltage is larger than a certain voltage.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.

Linearity is improved in an amplifier circuit without lowering gain. The amplifier circuit includes a transistor, a load, an impedance element, and a variable current source. The transistor amplifies an input signal. The load is connected between the transistor and a power supply. The impedance element is connected between the transistor and a ground terminal, and passes a direct current. The variable current source is connected to a connection part between the transistor and the impedance element, and supplies a current in accordance with a voltage of the connection part.

A transimpedance amplifier (TIA) circuit disclosed includes an input terminal, a first TIA circuit, a second TIA circuit, a field effect transistor (FET), and a gain control circuit. The first TIA circuit outputs a voltage signal from a first output in accordance with an input current received at a first input electrically connected to the input terminal. The second TIA circuit outputs a reference signal from a second output. The FET varies a resistance between a first current terminal and a second current terminal in accordance with a control signal applied to a control terminal. The first current terminal is electrically connected to the input terminal. The second current terminal is electrically connected to the second output of the second TIA circuit. The gain control circuit detects an amplitude of the voltage signal and generates the control signal according to a detection result of the amplitude.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

A fully differential rail-to-rail-output amplifier includes a differential input inverter pair, folded cascode pair, class AB control pair, and class AB output rail-to-rail pair. A drain associated with the folded cascode pair is operatively coupled to the class AB control pair, and the drain associated with the folded cascode pair is unconnected to the current source associated with the class AB control pair. A method of providing fully differential rail-to-rail-output amplification includes coupling a folded cascode pair operatively to a differential input inverter pair, coupling a drain associated with the folded cascode pair operatively to a class AB control pair, and coupling a class AB output rail-to-rail pair operatively to the class AB control pair.