According to one embodiment of the present invention, provided is an analog to digital converter. The analog-to-digital converter according to one embodiment of the present invention comprises an analog amplification unit and a flash conversion unit, wherein the analog amplification unit may have a structure in which in which two input terminal circuits that alternately operate share a single amplifier. Accordingly, the analog-to-digital converter according to one embodiment of the present invention can be implemented in a smaller area and operate at low power, and can have a high resolution while operating at a high speed.

In a preamplifier (amplifier) for the radiation detector, an interconnection layer connected to the bonding pad forms one electrode of a feedback capacitor. Since there is no wiring for connecting the bonding pad and capacitor, a parasitic capacitance caused by the wiring will not be generated. Moreover, the capacitor is arranged below the bonding pad with a conductive layer serving as the other electrode, so that the feedback capacitance of the capacitor is included in the parasitic capacitance between the interconnection layer and the substrate. Compared to the conventional case, an amount of capacitance corresponding to the parasitic capacitance caused by wiring and the feedback capacitance for the capacitor is reduced from the input capacitance. Thus, the input capacitance for the amplifying circuit is reduced.

An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.

A tuning fork sensor system places a controlled bias on the proof-mass drive-axis electrodes to cancel the quadrature charge. Also, its charge amplifiers employ a field-effect transistor biased slightly into the triode region so that it behaves as a very large value resistor. In addition, it uses a phase-locked loop having a special loop filter in order to optimize performance by rejecting off-frequency drive feedthrough to the motor pick-off while resulting in very low phase wander for the demodulation references.

A surface plasmon-based photodetector includes: a silicon substrate; a grating in contact with a surface of the silicon substrate, in which the grating forms a Schottky diode with the semiconductor substrate; and a complementary-metal-oxide-semiconductor (CMOS) sample and hold stage as well as an analog-to-digital circuit (ADC) in the silicon substrate and arranged to detect electrical current generated at the Schottky diode.

The present disclosure relates to a semiconductor device and a cell potential measuring device capable of improving measurement accuracy of a potential of a solution.A semiconductor device includes a read electrode that reads a potential of a solution, a differential amplifier, a first capacitor connected in series in a loop feeding back an output of the differential amplifier to a second input different from a first input from the read electrode, a resistance element connected in parallel with the first capacitor, and a second capacitor connected between a reference electrode indicating a reference potential and the second input. The present disclosure can be applied to, for example, a cell potential measuring device.

A circuit may include or may be coupled to a precharge structure to reduce or minimize a net perturbation, caused by switching, in the input source. Apparatus and techniques shown herein may enable low input current operation in a signal chain of an analog circuit by such reduction or minimization of such perturbation.

A current sensor architecture is implemented using a trans-resistance amplifier circuit having a low pass filter characteristic. The current sensing resistor and the input resistors for the amplifier circuit are matched thermally so that they have substantially identical temperature coefficients. The feedback resistors, which are coupled in parallel with corresponding capacitors, are implemented using switched capacitor circuits that emulate resistors. With this configuration, the current sensor is temperature insensitive.

The present invention provides an amplifier circuit, wherein the amplifier circuit includes an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone cancellation circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between an input node and an output node of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit includes a storage block including a switched-capacitor. The aliasing tone cancellation circuit is coupled between the input terminal of the amplifier circuit and the input node of the amplifier, and configured to generate a signal to cancel or reduce an aliasing tone of the feedback signal according to the input signal.

The present disclosure discloses a switched capacitor amplifier apparatus for improving level-shifting. An amplifier includes input terminals and output terminals. Two capacitor circuits correspond to signal input terminals and signal output terminals and each includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor. The sampling capacitor circuit samples an input signal from one of the signal input terminals to one of the input terminals. An electrical charge neutralizing capacitor is coupled between the output terminals. The load capacitor and the level-shifting capacitor are charged according to an output from one of the output terminals in an estimation period. The level-shifting capacitor charges the load capacitor in a level-shifting period to generate an output signal at one of the signal output terminals. The electrical charge neutralizing capacitor receives and provides electrical charges from the output terminals to the level-shifting capacitor respectively in the estimation period and the level-shifting period.