A multi-voltage power generation circuit is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltages can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.

A multi-voltage power generation circuit is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltages can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.

Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.

This application provides an operational amplifier that increases the stability and settling speed of a common-mode feedback circuit. The operational amplifier includes N stages of amplifiers connected in series and M common-mode feedback circuits, where N and M are integers, N≥3, and N≥M>1. An i.sup.th common-mode feedback circuit in the M common-mode feedback circuits is configured to: detect a common-mode output voltage of a (j+b).sup.th stage of amplifier, and regulate an electrical parameter of at least one of the j.sup.th stage of amplifier to the (j+b).sup.th stage of amplifier, to stabilize the common-mode output voltage of the (j+b).sup.th stage of amplifier. An M.sup.th common-mode feedback circuit is configured to detect and stabilize a common-mode output voltage of an N.sup.th stage of amplifier. Herein i, j, and b are integers, M≥i≥1, N≥j≥1, i≥j, j+b≤N, and b≥0.

Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.

A circuit comprises: a circuit input; a circuit output; at least one passive feedback loop coupled between the circuit output and the circuit input; an active element, coupled in a feed-forward path of the circuit between the circuit input and the circuit output and configured to drive the at least one feedback loop in order to establish a function of the circuit, wherein the feed-forward path of the circuit comprises a second node (Vx) and a first node which are internal nodes of the active element and which are coupled between the circuit input and the circuit output, wherein the first node is configured to have a first voltage, the first voltage being a function of the circuit output, wherein the active element comprises a first voltage drop element coupled between the second node (Vx) and the first node.

A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

A circuit comprises: a circuit input; a circuit output; at least one passive feedback loop coupled between the circuit output and the circuit input; an active element, coupled in a feed-forward path of the circuit between the circuit input and the circuit output and configured to drive the at least one feedback loop in order to establish a function of the circuit, wherein the feed-forward path of the circuit comprises a second node (Vx) and a first node which are internal nodes of the active element and which are coupled between the circuit input and the circuit output, wherein the first node is configured to have a first voltage, the first voltage being a function of the circuit output, wherein the active element comprises a first voltage drop element coupled between the second node (Vx) and the first node.

Described herein is a preamplifier circuit for a capacitive acoustic transducer provided with a MEMS detection structure that generates a capacitive variation as a function of an acoustic signal to be detected, starting from a capacitance at rest; the preamplifier circuit is provided with an amplification stage that generates a differential output signal correlated to the capacitive variation. In particular, the amplification stage is an input stage of the preamplifier circuit and has a fully differential amplifier having a first differential input (INP) directly connected to the MEMS detection structure and a second differential input (INN) connected to a reference capacitive element, which has a value of capacitance equal to the capacitance at rest of the MEMS detection structure and fixed with respect to the acoustic signal to be detected; the fully differential amplifier amplifies the capacitive variation and generates the differential output signal.

A differential input stage includes first and second input transistors with current flow paths are coupled between a tail transistor current flow path and first and second nodes, respectively. An output stage includes first and second output transistors having current flow paths between a supply line and first and second output nodes, respectively, coupled to the first and second nodes. First and second common-mode control transistors have current flow paths jointly coupled to a ground current flow path of a common-mode tail transistor. The first common-mode control transistor has a control terminal resistively coupled to the first and second output nodes. A bias duplicate transistor has a current flow path arranged in a bias current flow line between the supply line and ground. The bias duplicate transistor is coupled in a 1:N current mirror arrangement with the tail transistor in the differential input stage.