Patent classifications
H03F2203/5031
LEVEL CONVERTER AND CIRCUIT ARRANGEMENT COMPRISING SUCH LEVEL CONVERTERS
A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.
Level converter and circuit arrangement comprising such level converters
A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.
Transconductance current source
A transconductance circuit has an input terminal (V.sub.IN) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (V.sub.IN); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit provides a lower bias voltage for the second current source than for the first current source.
TRANSCONDUCTANCE CURRENT SOURCE
A transconductance circuit has an input terminal (V.sub.IN) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (V.sub.IN); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit provides a lower bias voltage for the second current source than for the first current source.
FILTER CIRCUITRY AND CIRCUITRY COMPRISING THE SAME
Polyphase filter circuitry including: an input node to receive an input signal V.sub.IN having a dominant frequency f.sub.PPF; and a common-source amplifier circuit. The common-source amplifier circuit includes a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor C.sub.PFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance R.sub.M1 at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor C.sub.PFF are define the frequency response of the common-source amplifier circuit so that, based on the input signal V.sub.IN, a signal V.sub.LEAD is generated at the drain terminal of the transistor M1 which leads the input signal V.sub.IN in phase by a given phase shift .sub.LEAD and a signal V.sub.LAG is generated at the source terminal of the transistor M1 which lags the input signal V.sub.IN in phase by a given phase shift .sub.LAG.