A power control method for a charging system includes: detecting a power signal and an input voltage of the power signal; determining a charging protocol supported by the power signal; and determining whether to conduct a power switching circuit or not according to the input voltage of the power signal and the charging protocol supported by the power signal to provide power for an amplifier chip of the charging system.

A power control method for a charging system includes: detecting a power signal and an input voltage of the power signal; determining a charging protocol supported by the power signal; and determining whether to conduct a power switching circuit or not according to the input voltage of the power signal and the charging protocol supported by the power signal to provide power for an amplifier chip of the charging system.

An impedance matching circuit includes a radiofrequency terminal and a series circuit connected to the radiofrequency terminal, wherein the series circuit comprises at least one reactance and at least one switching element having a drive input. A drive circuit is connected to the drive input and a coupler is connected to the drive circuit so as to an enable signal input. The impedance matching circuit enables short switching times and low losses in the at least one switching element.

Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

In an embodiment a circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.

In an embodiment a circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.

A power amplifier circuit includes an amplifier that amplifies an input signal RFin, a matching circuit that provides impedance matching between an output port of the amplifier and an output terminal, an input of the matching circuit being connected to the output port of the amplifier, an output of the matching circuit being connected to the output terminal, and a resonant circuit provided between ground and a signal path that connects the output port of the amplifier and the input of the matching circuit, the resonant circuit resonating at a resonant frequency greater than or equal to the frequency of a fourth harmonic wave of an amplified signal obtained by amplifying the input signal.

A power amplifier circuit includes an amplifier that amplifies an input signal RFin, a matching circuit that provides impedance matching between an output port of the amplifier and an output terminal, an input of the matching circuit being connected to the output port of the amplifier, an output of the matching circuit being connected to the output terminal, and a resonant circuit provided between ground and a signal path that connects the output port of the amplifier and the input of the matching circuit, the resonant circuit resonating at a resonant frequency greater than or equal to the frequency of a fourth harmonic wave of an amplified signal obtained by amplifying the input signal.

Embodiments of the present disclosure include a harmonic power amplifying circuit with high efficiency and high bandwidth and a radio-frequency power amplifier. The circuit comprises an input matching network (11), a transistor (M), and an output matching network (12); a gate of the transistor (M) connected to an output end of the input matching network (11), a drain thereof connected to an input end of the output matching network (12), and a source thereof being grounded; wherein the output matching network (12) enables a lower sideband of the harmonic power amplifying circuit to work in a continuous inverse F amplification mode and an upper sideband of the harmonic power amplifying circuit to work in a continuous F amplification mode; wherein the output matching network (12) and a parasitic network of the transistor (M) form a low pass filter. By transitioning from the continuous inverse F power amplifier working mode to the continuous F power amplifier working mode, the efficiency of a continuous harmonic control power amplifier is effectively improved to be higher than 60%, a relative bandwidth is improved to be higher than 80%, and the harmonic impedance is simple to match and easy to realize.