In the amplifier circuit, the rising settling time and the falling settling time are kept short. The amplifier circuit includes a first transistor of a first conductivity type having a first control terminal; a second transistor of a second conductivity type different from the first conductivity type, the second transistor having a second control terminal connected to an input terminal and a fourth current terminal connected to the first control terminal; a third transistor; and a fourth transistor of a fourth conductivity type different from the first conductivity type, the fourth transistor having a fourth control terminal connected to the first control terminal at an equal potential, and a seventh current terminal connected to a third fixed potential.

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

An automated testing system comprises a high side switch circuit coupled to an input/output (I/O) connection, a low side switch circuit coupled to the I/O connection, a high side force amplifier (HFA) coupled to the high side switch, a low side force amplifier (LFA) coupled to the low side switch, an adjusting circuit coupled to the HFA and the LFA, and a control circuit configured to change the adjusting circuit to change control of current at the I/O connection from one of the HFA or LFA to the other of the HFA or LFA.

A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

A current-bootstrap comparator includes a receiving unit, a first current generation unit and a second current generation unit. The receiving unit receives a load voltage signal, a low threshold voltage and a high threshold voltage. The first current generation unit generates a first current. The second current generation unit generates a second current having a magnitude substantially same as a magnitude of the first current and a direction reverse to the first current. The first current and the second current are supplied to a next-stage circuit as a source current and a corresponding sink current, respectively, when the level of the load voltage signal is higher than the high threshold voltage or lower than the low threshold voltage. The magnitudes of the first current and the second current substantially equal zero when the level of the load voltage signal is between the high threshold voltage and the low threshold voltage.

The series regulator has: a differential amplifier; a level shifter including a level shift transistor with a drain connected to a gate; and a source follower including an output transistor. The differential amplifier includes an amplification stage having a non-inverting input terminal for input of a reference voltage, an inverting input terminal for input of a feedback voltage, and an amplifier output terminal. The differential amplifier has a DC operation point where an error of an output voltage at the amplifier output terminal to an input voltage to the non-inverting input terminal is equal to or under a gate-source voltage of an input transistor, and a follower output terminal of the source follower is feedback-connected to the inverting input terminal. The level shifter performs a level shift to make an output voltage of the source follower coincident with the voltage at the amplifier output terminal of the differential amplifier.

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

One example includes an amplifier system. The amplifier system includes an input stage configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The amplifier system also includes an amplifier stage that receives at least one power voltage and is configured to amplify the reference voltage pulse and to provide pulse-shaping of the amplified reference voltage pulse based on a change of amplitude of the at least one power voltage resulting from an amplitude of the reference voltage pulse.