An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

Disclosed is a transimpedance amplifier, comprising a first-stage trans-conductance amplifier TCA, a second-stage TCA, a third-stage amplifier and a feedback circuit. The first-stage TCA is electrically connected to an input current source to receive a first input signal, and outputs a first output signal. The second-stage TCA is electrically connected to the first-stage TCA to receive the first output signal, and outputs a second output signal. The third-stage amplifier is electrically connected to the second-stage TCA to receive the second output signal, and outputs a third output signal. One end of the feedback circuit is electrically connected to the input of the first-stage TCA, and the other end of the feedback circuit is electrically connected to the output of the third-stage amplifier to stabilize the third output signal. The third-stage amplifier is composed of a first output stage and a second output stage.

An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

One embodiment describes a transimpedance amplifier (TIA) system. The system includes an inverter TIA stage interconnecting an input node and an output node and configured to invert an input signal at the input node to provide a first inverted signal component at the output node. The system also includes a noise-canceling inverter stage arranged in parallel with the inverter stage and being configured to invert the input signal to provide a second inverted signal component and to invert noise from the input node. Thus, the first and second inverted signal components constructively combine at the output node and the noise is substantially mitigated at the output node.