The present disclosure relates to chopper amplifier circuits with inherent chopper ripple suppression. Example implementations can realize a doubly utilized chopper amplifier circuit that is a current-saving circuit with a wake-up function that is capable of providing a self-wake signal in order to change into a fast, low-jitter/low-latency mode, and to provide a wake-up signal for a sleeping microprocessor or a system in response to signal changes.

The present disclosure relates to chopper amplifier circuits with inherent chopper ripple suppression. Example implementations can realize a doubly utilized chopper amplifier circuit that is a current-saving circuit with a wake-up function that is capable of providing a self-wake signal in order to change into a fast, low-jitter/low-latency mode, and to provide a wake-up signal for a sleeping microprocessor or a system in response to signal changes.

According to one embodiment, a chopper stabilized amplifier includes an input unit, a first chopper, a first amplifier, and a switch circuit. The input unit receives a differential input signal at a first input terminal and a second input terminal. The first chopper modulates the differential input signal based on a first control signal and an inverse signal of the first control signal. The first amplifier amplifies the signals with the modulated differential output from the first chopper. The switch circuit is provided between the input unit and the first chopper, and receives a second control signal and reduces input currents which flow in the first chopper when the first chopper performs a modulating operation, by using an operation with the second control signal.

According to one embodiment, a chopper stabilized amplifier includes an input unit, a first chopper, a first amplifier, and a switch circuit. The input unit receives a differential input signal at a first input terminal and a second input terminal. The first chopper modulates the differential input signal based on a first control signal and an inverse signal of the first control signal. The first amplifier amplifies the signals with the modulated differential output from the first chopper. The switch circuit is provided between the input unit and the first chopper, and receives a second control signal and reduces input currents which flow in the first chopper when the first chopper performs a modulating operation, by using an operation with the second control signal.

An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.

Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2.sup.N amplifiers where N is a positive integer. By the capacitive sensor chip based on the power-aware dynamic charge-domain amplifier array, utilization efficiency of charges can be effectively improved, power consumption overheads nay be effectively saved, energy efficiency of a system is greatly improved and a driving capability of the subsequent-stage amplifier may be adaptively distributed according to the size of an input capacitance.

Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.

Embodiments of the present disclosure provide a chopper amplifier circuit that includes an operational amplifier, and a notch filter to be operated by a chopping pulse. The notch filter has a first branch that has a first capacitor, and a second branch that has a second capacitor. A chopping delay switch is connected to the first branch and the second branch of the notch filter. A control circuit is to close the chopping delay switch to short-circuit the first branch and the second branch of the notch filter to each other. The control circuit is to detect establishment of feedback signal at the chopper amplifier. The control circuit is to open the chopping delay switch, responsive to detecting establishment of the feedback signal at the chopper amplifier.

An amplifier includes: a signal polarity inversion circuit which modulates an input signal and outputs a modulation signal; an amplifier circuit which is constituted from an operational transconductance amplifier (OTA) to amplify the modulation signal and output a current; and a sample-hold circuit having a sampling capacitor which is charged and discharged by selective sampling of the output current of the amplifier circuit and a holding capacitor to which the voltage of the sampling capacitor is transferred.

A device for analysis of cells comprises: an active sensor area (104) presenting a surface for cell growth; a microelectrode array (102) comprising a plurality of pixels (110) in the active sensor area (104), wherein each pixel (110) comprises at least one electrode (120) at the surface, wherein each pixel (110) is configured to control the configuration of the pixel circuitry and set a measurement modality of the pixel; recording circuitry having a plurality of recording channels (130), wherein each pixel (110) is connected to a recording channel (130), wherein each recording channel (130) comprises a reconfigurable component (131), which is selectively controlled between being set to a first mode, in which the reconfigurable component (131) is configured to amplify a received pixel signal, and being set to a second mode, in which the reconfigurable component (131) is configured to selectively pass a frequency band of the received pixel signal.