An amplifier circuit includes a primary differential amplifier circuit connected to receive a differential input and provide a primary differential output with a first non-linearity. A secondary differential amplifier circuit is connected to receive the differential input. The secondary differential amplifier circuit is configured to generate a secondary differential output with a second non-linearity. The secondary differential output and the primary differential output are coupled together with opposing polarities such that the second non-linearity cancels out at least the first non-linearity.

An apparatus for canceling an input offset of a receiver including a differential amplification unit and a differential comparison unit in a distance sensing system includes: an output monitoring unit selectively monitoring differential outputs of the differential comparison unit and the differential amplification unit; a current type digital-analog conversion unit connected to each of an input terminal of the differential comparison unit and the input terminal of the differential amplification unit; and a control unit controlling the current type digital-analog conversion unit to reduce a difference in differential output of the differential comparison unit according to a comparison result for the difference of the monitored differential output of the differential comparison unit and controlling the current type digital-analog conversion unit to reduce the difference in differential output of the differential amplification unit according to the comparison result for the difference of the monitored differential output of the differential amplification unit.

Provided is a reception circuit that suppresses skew of a waveform of a signal and enables high-speed data communication.

A reception circuit according to the present disclosure includes: a first differential stage that receives a first input signal and a second input signal at a first input unit and a second input unit, respectively, and causes first and second currents corresponding to the first and second input signals, respectively, to flow; a second differential stage including a first current path that generates and outputs a first amplified signal corresponding to the first current and a second current path that generates and outputs a second amplified signal corresponding to the second current; a power supply line that supplies power to the first and second differential stages; and at least one variable resistance unit provided in the first or second current path.

The present invention is gallium nitride based operational amplifier because reliability and performance of the gallium nitride is better than the silicon counterpart in radiation environment. The operational amplifier includes four stages, first stage is dual input balanced output differential amplifier, second stage is dual input unbalanced differential amplifier, third stage is buffer stage to couple second and fourth stage, and fourth stage is cascaded common source amplifier with degeneration. A capacitor coupled between second and third stage is to enhance the stability of operational amplifier.

An operational amplifier includes a differential amplifier circuit and a common mode feedback circuit. The differential amplifier circuit includes a bias circuit, an amplifier circuit, and a load circuit. The bias circuit generates a first operation voltage. The amplifier circuit receives a pair of input signals, and generates a pair of output signals according to the input signals and the first operation voltage. The load circuit is coupled to the amplifier circuit. The common mode feedback circuit generates at least one common mode feedback voltage based on a common mode voltage and a reference voltage. The common mode voltage is associated with the output signals. The at least one common mode feedback voltage is for controlling the bias circuit and the load circuit, to control a direct current (DC) voltage level of the differential amplifier circuit.

A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

An amplifier circuit includes multiple transistors, a set of input routing circuits, and a set of output routing circuits. Each output routing circuit corresponds to an input routing circuit. Each input routing circuit and its corresponding output routing circuit are controlled by one or more control signals. Each input routing circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal of the amplifier circuit, a second input terminal of the amplifier circuit, or a third input terminal of the amplifier based on a value of the one or more control signals. Each output routing circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal of the amplifier circuit, a second output terminal of the amplifier circuit, or a calibration circuit based on the value of the one or more control signals.

A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.

A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals.

Variations in a receiving circuit employing differential signaling are reduced. The receiving circuit converts a first signal and a second signal which are supplied through differential signaling into a third signal which is a single-ended signal and outputs the third signal. The receiving circuit includes an operational amplifier, a first element, a first transistor, and a first circuit. The first element is connected to the first circuit through a first node to which the first transistor is connected. The first signal and the second signal that is the inverse of the first signal are supplied to the operational amplifier. The operational amplifier supplies an output signal to the first element, and a first preset potential is supplied to the first node through the first transistor. A signal including variations of the operational amplifier is stored in the first element in accordance with the first preset potential. The first circuit that is supplied with the first preset potential determines an initial value of the third signal without being influenced by the signal including variations of the operational amplifier.