Sense amplifier (amp) circuitry for an implantable stimulator device is disclosed useful for sensing neural responses or other voltages in a patient's tissue. The sense amp circuitry comprises a low-voltage and a high-voltage sense amp circuit, either of which may be selected based on an assessment of the magnitude of the voltage at either or both of the inputs connected to selected sensing electrodes. The assessed magnitude, as determined by monitoring circuitry, can be processed by an algorithm to select use of one of the sense amp circuits, selecting the low-voltage sense amp circuit when the magnitude(s) are lower, and the high-voltage sense amp circuit when the magnitude(s) are higher. Furthermore, DC offset compensation circuitry is disclosed to equate the DC levels of the inputs, which may only operate when the high-voltage sense amp is selected.

A power amplifier (PA) linearization technique with a wider linearized power range is proposed. Proposed two types of linearizers with cross-coupled PMOS and NMOS configuration. The idea is to use a complimentary device compared with the PA core device, and the behavior of Cgs of the linearizer are also complimentary to the PA itself. In the other words, the overall Cgs of the PA with the linearizer would be constant without leading to non-linear waveform. Both linearizers can effectively compensate not only AMAM but also AMPM. First type of linearizer can be integrated with PA cores, and second type of linearizer can be used in the IMN. Both linearizers have effective IM3 reduction in different corner.

A motion sensor device comprises: a reverse electrowetting-on-dielectric (REWOD) generator configured to generate alternating current (AC) based on motion; a motion sensor configured to measure motion data; and a wireless motion sensor read-out circuit coupled to the REWOD generator and the motion sensor, the wireless motion sensor read-out circuit configured to transmit the motion data and operate on the AC from the REWOD generator.

A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.

Receiver circuitry to convert a pulse-width-modulated (PWM) signal into a digital data signal includes analog-to-digital converter circuitry that converts the PWM signal into an intermediate signal, a timing generator that derives control signals from the intermediate signal, analog charge storage circuitry that is charged and discharged according to the control signals, and circuitry that derives a digital output signal from an analog waveform output by the charge storage circuitry. The charge storage circuitry includes a capacitance and a current-limiting element, one of which is variable to control a time constant of the charge storage circuitry for calibration to a data rate of the PWM signal. A control signal may be single-ended and compared to a threshold, or may be differential with the legs compared to each other. The output is derived on a falling clock edge, and maintained until a subsequent falling clock edge.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

The apparatus relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long-Term Evolution (LTE). The disclosure relates to an apparatus including an electronic circuit for amplifying a signal. The apparatus includes a transceiver including an amplification circuit, and at least one processor coupled to the transceiver. The amplification circuit includes a first path to generate a first current corresponding to a voltage of an input signal, a second path to generate a second current corresponding to a voltage of the input signal, a separation unit to control each of the first current and the second current, a current mirror to generate a third current corresponding to the first current, and a folding unit to generate an output signal on the basis of the second current and the third current.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.