An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

Wideband power combiners and splitters are provided herein. In certain embodiments, a power combiner/splitter is implemented with a first coil connecting a first port and a second port, and a second coil connecting a third port and a fourth port. The first coil and the second coil are inductively coupled to one another. For example, the first coil and the second coil can be formed using adjacent conductive layers of a semiconductor chip, an integrated passive device, or a laminate. The power combiner/splitter further includes a fifth port tapping a center of the first coil and a sixth port tapping a center of the second coil. The fifth port and the sixth port serve to connect capacitors and/or other impedance to the center of the coils to thereby provide wideband operation.

Disclosed is a reconfigurable power amplifier having a 2.sup.N−1 number of input-side reconfigurable quadrature couplers connected in a tree structure, wherein a 2.sup.(N−1) number of the input-side reconfigurable quadrature couplers have coupler output terminals, and a root of the tree structure is one of the input-side reconfigurable quadrature couplers having a main input terminal. Also included is a 2.sup.N−1 number of output-side reconfigurable quadrature couplers connected in a tree structure, wherein a 2.sup.(N−1) number of the output-side reconfigurable quadrature couplers have coupler input terminals, and a root of the tree structure is one of the output-side reconfigurable quadrature couplers having a main output terminal. Further included is a 2.sup.N number of constituent amplifiers divided into amplifier pairs having amplifier input terminals connected to corresponding ones of the coupler output terminals and having amplifier output terminals coupled to corresponding ones of the coupler input terminals.

Provided is a high-gain amplifier based on double-gain boosting including a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

An RF amplifier utilizes first and second main amplifiers in a balanced amplifier configuration with first and second auxiliary amplifiers connected in parallel across the first and second main amplifiers, respectively. The main and the auxiliary amplifiers are biased such that the third-order nonlinearity components in the combined output current are reduced. A common or independent bias control circuit(s) control(s) the DC operating bias of the auxiliary amplifiers and establishes DC operating points on curves representing third-order nonlinear components within the drain current having a positive slope (opposite to the corresponding slope of the main amplifiers). This results in reduction of overall third-order nonlinear components in combined currents at the output. In another embodiment, a phase shift of an input to one auxiliary amplifier is used to provide a peak in minimization at a frequency associated with the phase shift.

A power amplifier circuit includes a first impedance transformer circuit arranged to connect with a carrier device, and a second impedance transformer circuit arranged to connect with a peaking device. Both the first and the second impedance transformer circuit include a parallel impedance transformer arrangement.

A power amplifier arrangement (100) for amplifying an input signal (Pin) to produce an output signal (Pout) is disclosed. The amplifier arrangement (100) comprise an input port (IN) for receiving the input signal; an output transmission line (110) having a first terminal (111) and a second terminal (112); an output port (OUT) coupled to the second terminal (112) of the output transmission line (110) for providing the output signal; and a plurality N of amplifying devices (121, 122, . . . 12N) distributed along the output transmission line (110). The power amplifier arrangement (100) is configured such that the plurality N of amplifying devices are active sequentially for amplifying the input signal with increasing amplitude of the input signal.

Methods and apparatus are provided. In an example aspect, a method of operating an amplifier circuit is provided. The amplifier circuit comprises a first amplifier configured to receive a first signal, a balanced amplifier comprising second and third amplifiers and configured to receive a second signal, and a first directional coupler. An output of the first amplifier is connected to a transmitted port of the first directional coupler, an output of the second amplifier is connected to an input port of the first directional coupler, an output of the third amplifier is connected to an isolated port of the first directional coupler, and a coupled port of the first directional coupler is connected to an output of the amplifier circuit. The method comprises operating the amplifier circuit in a first output peak amplitude range of the amplifier circuit wherein, in the first output peak amplitude range, the first signal is based on a signal to be amplified and has an amplitude that increases across the first output peak amplitude range from substantially zero to a first amplitude, and the second signal is substantially zero, and operating the amplifier circuit in a second output peak amplitude range of the amplifier circuit, wherein the second output peak amplitude range is higher than the first output peak amplitude range and wherein, in the second output peak amplitude range, the first signal is based on the signal to be amplified and has an amplitude that decreases across the second output peak amplitude range from the first amplitude to a second amplitude, and the second signal is based on the signal to be amplified and has an amplitude that increases across the second output peak amplitude range from a third amplitude to a fourth amplitude.

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.