A pseudo resistance circuit is disclosed that is capable of suppressing fluctuation in resistance value with fluctuation in process or temperature and facilitating adjustment. The pseudo resistance circuit includes a first MOSFET, a second MOSFET, a first current source which generates a first current substantially proportional to absolute temperature, and voltage source which generates a first voltage, which is a substantially linear function of absolute temperature. The gate of the first MOSFET and the gate of the second MOSFET are connected together, the second MOSFET is diode-connected, the first current is supplied to the drain of the second MOSFET, the first voltage is applied to the source of the second MOSFET, and a resistor having a resistance value according to the gate voltage of the first MOSFET is formed between the drain and the source of the first MOSFET.

A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

A pseudo resistance circuit is disclosed that is capable of suppressing fluctuation in resistance value with fluctuation in process or temperature and facilitating adjustment. The pseudo resistance circuit includes a first MOSFET, a second MOSFET, a first current source which generates a first current substantially proportional to absolute temperature, and voltage source which generates a first voltage, which is a substantially linear function of absolute temperature. The gate of the first MOSFET and the gate of the second MOSFET are connected together, the second MOSFET is diode-connected, the first current is supplied to the drain of the second MOSFET, the first voltage is applied to the source of the second MOSFET, and a resistor having a resistance value according to the gate voltage of the first MOSFET is formed between the drain and the source of the first MOSFET.

A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0. The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.