A resampling method based on window function for flexible sampling rate conversion in broadband frequency measurement devices is described. The resampling algorithm can satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are analyzed, and the design criterion of the filter in resampling model is considered. A fractional delay filter design model based on window function method is described. A fractional delay filter matrix, which is expressed by polynomial form, is constructed. Then the expression related to subfilter coefficients is obtained and subfilter coefficients are solved for by the least square method.

A resampling method based on window function for flexible sampling rate conversion in broadband frequency measurement devices is described. The resampling algorithm can satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are analyzed, and the design criterion of the filter in resampling model is considered. A fractional delay filter design model based on window function method is described. A fractional delay filter matrix, which is expressed by polynomial form, is constructed. Then the expression related to subfilter coefficients is obtained and subfilter coefficients are solved for by the least square method.

The present application discloses a filtering method and a filtering device of a filter, a filter and a storage medium. The method includes: obtaining a clock input signal and a clock output signal and comparing them, and determining a phase relationship between the clock input signal and the clock output signal according to a comparison result; determining a decimal deviation factor according to the phase relationship in determining that the phase relationship meets a preset condition; and filtering a sample input signal according to the decimal deviation factor to obtain a filtered sample output signal. The present application can obtain an accurate decimal deviation factor, by obtaining the phase relationship between the clock input signal and the clock output signal, in determining that the phase relationship meets a preset condition, and can adjust the sample input signal according to the decimal deviation factor to obtain a smooth sample output signal.

A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

Systems and method for resampling are provided. A method of resampling includes receiving a first sampled signal that is sampled at a first sample rate, where the first sample rate is a submultiple of a system clock rate for a Farrow filter. The method further includes resampling the first sampled signal, using the Farrow filter having a plurality of finite impulse response (FIR) filters and an arbitrary position interpolator, at a second sample rate to generate a second sampled signal. The interpolation factor for each sample of the second sampled signal is retrieved from at least one lookup table stored in memory and the first sample rate and the second sample rate are fixed and locked to a common frequency reference. The method further includes outputting the second sampled signal at the second sample rate.

Systems and method for resampling are provided. A method of resampling includes receiving a first sampled signal that is sampled at a first sample rate, where the first sample rate is a submultiple of a system clock rate for a Farrow filter. The method further includes resampling the first sampled signal, using the Farrow filter having a plurality of finite impulse response (FIR) filters and an arbitrary position interpolator, at a second sample rate to generate a second sampled signal. The interpolation factor for each sample of the second sampled signal is retrieved from at least one lookup table stored in memory and the first sample rate and the second sample rate are fixed and locked to a common frequency reference. The method further includes outputting the second sampled signal at the second sample rate.

Systems and methods are provided in which a wireless receiver can be configured to digitally synchronize a receive sampling rate to a transmit sampling rate, and may include a digital interpolator controlled by a timing control unit with a timing offset estimator. The timing control unit can be configured to calculate and output parameters to the digital interpolator. The digital interpolator can include a sample buffer followed by a fractional delay filter. Output parameters to the digital interpolator can include a fractional delay timing offset signal of the receiver relative to a transmitter timing signal and a buffer pointer control signal to control a position of the read pointer relative to a write pointer to compensate for subsample timing offset. The timing offset estimator can be configured to calculate and provide to the timing control unit a sampling period ratio control word and an instantaneous timing offset control word.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

Systems (400) and methods for removing dither introduced into a transmitted RF signal. The method comprising: receiving, by a receiver, the transmitted RF signal; converting, by the receiver, the transmitted RF signal into a discrete-time IF signal comprising a sequence of samples, where at least a first sample of said samples has a first sample duration different than a second sample duration of at least a second sample of said samples; and performing operations by a sub-sample dither removal device of the receiver to modify a sample timing of the discrete-time IF signal by decreasing or increasing the first sample duration of the first sample using a digital signal processing technique in a digital domain.