Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.

A digital filter for filtering an input signal to form an output signal containing a coefficient multiplier and a moving-average filter. The coefficient multiplier is embodied to multiply values of the input signal by coefficients of the filter to form an intermediate signal. The moving-average filter is embodied to generate the output signal as a moving average of the intermediate signal.

A filter is disclosed. The filter includes at least one first multiplication approximation unit, for approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bit-wise shift operation; and at least one second multiplication approximation unit, for approximating at least one second multiplication operation corresponding to at least one second coefficient with a plurality of second bit-wise shift operations and at least one addition operation.

A hardware downscaler and an architecture for implementing a FIR filter in which the downscaler can be arranged for downscaling by a half in one dimension. The downscaler can comprise: hardware logic implementing a first three-tap FIR filter; and hardware logic implementing a second three-tap FIR filter; wherein the output from the hardware logic implementing the first three-tap filter is provided as an input to the hardware logic implementing the second three-tap filter.

A filter is disclosed. The filter includes at least one first multiplication approximation unit, for approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bit-wise shift operation; and at least one second multiplication approximation unit, for approximating at least one second multiplication operation corresponding to at least one second coefficient with a plurality of second bit-wise shift operations and at least one addition operation.

A hardware downscaling module and downscaling methods for downscaling a two-dimensional array of values. The hardware downscaling unit comprises a first group of one-dimensional downscalers; and a second group of one-dimensional downscalers; wherein the first group of one-dimensional downscalers is arranged to receive a two-dimensional array of values and to perform downscaling in series in a first dimension; and wherein the second group of one-dimensional downscalers is arranged to receive an output from the first group of one-dimensional downscalers and to perform downscaling in series in a second dimension.

Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.

A method includes receiving an input digital signal and applying the input digital signal to digital filter processing with a corner frequency to produce a filtered output digital signal. The digital filter processing includes a set of multiplication operations using a set of filter multiplication coefficients. The set of multiplication operations is performed by alternately using a first set of approximate multiplication coefficients and a second set of approximate multiplication coefficients different from the first set of approximate multiplication coefficients. The approximate multiplication coefficients in the first set of approximate multiplication coefficients and the second set of approximate multiplication coefficients approximate multiplication coefficients in the set of filter multiplication coefficients as a function of negative power-of-two values. The alternating of multiplication operations results in digital filter processing with average corner frequency approximating the corner frequency.

Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.

Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.