H03H17/0238

HIGH-RATE DECIMATION FILTER WITH LOW HARDWARE COMPLEXITY

A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.

Method for simplifying a filter and associated devices
11762059 · 2023-09-19 · ·

The invention relates to a method for simplifying a sampled signal digital filter, the method including at least one step for: in order to obtain a first intermediate filter, gathering channels including discrete nonstationary operations relating to the same signal, the first channels including the nonstationary operations relating to a first signal and the second channels including the nonstationary operations relating to a second signal, in order to obtain a second intermediate filter, on each of the first channels and second channels, commutative stationary operations with the nonstationary operations, in order to eliminate the redundant nonstationary operations, and building the filter corresponding to the last obtained intermediate filter.

Method for filtering with zero latency and associated devices
11223380 · 2022-01-11 · ·

The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method including at least one step for: obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2.sup.p points on a signal coming from the input signal, the integer p being greater than or equal to 1, applying an inverse discrete Fourier transform to M/2.sup.p points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

Generating a representation of high-frequency electric power delivery system data using deviations from a trend

A system, method, and computer program product are provided for representation of high-frequency signal data. In use, input data is received including high-frequency signals, wherein the input data is of a first width. Next, the input data is processed to manage display of the input data, where specifically the input data is divided into one or more segments based on first criteria including the first width, and from each segment of the one or more segments, a maximum value is identified and a minimum value is identified. The maximum and minimum may be trend maximum and minimum values. The input data is transformed to a visualizable representation of the high-frequency signals, the visualizable representation of the high-frequency signals including a plot of the maximum value and the minimum value for each segment of the one or more segments. Additionally, the plot is displayed.

METHOD FOR FILTERING WITH ZERO LATENCY AND ASSOCIATED DEVICES
20210119655 · 2021-04-22 ·

The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method including at least one step for: obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2.sup.p points on a signal coming from the input signal, the integer p being greater than or equal to 1, applying an inverse discrete Fourier transform to M/2.sup.p points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

METHOD FOR SIMPLIFYING A FILTER AND ASSOCIATED DEVICES
20210116534 · 2021-04-22 ·

The invention relates to a method for simplifying a sampled signal digital filter, the method including at least one step for: in order to obtain a first intermediate filter, gathering channels including discrete nonstationary operations relating to the same signal, the first channels including the nonstationary operations relating to a first signal and the second channels including the nonstationary operations relating to a second signal, in order to obtain a second intermediate filter, on each of the first channels and second channels, commutative stationary operations with the nonstationary operations, in order to eliminate the redundant nonstationary operations, and building the filter corresponding to the last obtained intermediate filter.

METHOD FOR FILTERING WITH REDUCED LATENCY AND ASSOCIATED DEVICES
20210117498 · 2021-04-22 ·

The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method including at least one step for: obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2 points on a signal coming from the input signal, applying an inverse discrete Fourier transform to M/2 points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

GENERATING A REPRESENTATION OF HIGH-FREQUENCY ELECTRIC POWER DELIVERY SYSTEM DATA USING DEVIATIONS FROM A TREND

A system, method, and computer program product are provided for representation of high-frequency signal data. In use, input data is received including high-frequency signals, wherein the input data is of a first width. Next, the input data is processed to manage display of the input data, where specifically the input data is divided into one or more segments based on first criteria including the first width, and from each segment of the one or more segments, a maximum value is identified and a minimum value is identified. The maximum and minimum may be trend maximum and minimum values. The input data is transformed to a visualizable representation of the high-frequency signals, the visualizable representation of the high-frequency signals including a plot of the maximum value and the minimum value for each segment of the one or more segments. Additionally, the plot is displayed.

High-rate decimation filter with low hardware complexity

A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.

FIR filter circuit design method using approximate computing

A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.