The present invention provides an actually-measured marine environment data assimilation method based on sequence recursive filtering three-dimensional variation. The method includes: preprocessing actually-measured marine environment data; calculating a target function value; calculating a gradient value of a target function; calculating a minimum value of the target function; extracting space multi-scale information from the actually-measured data; and updating background field data to form a final data assimilation analysis field. The present invention improves the traditional recursive filtering three-dimensional variation method, and sequentially assimilates information with different scales, thereby effectively overcoming the problem that multi-scale information cannot be effectively extracted by a traditional three-dimensional variation method. A high-order recursive Gaussian filter is used, and a cascaded form of the high-order recursive filter is converted into a parallel structure, so that the recursive filtering process of the recursive Gaussian filter can be executed in parallel, and many problems caused by a cascaded filter are overcome.

A storage apparatus of an associative array type that stores a large-sized value at a low cost is provided. The storage apparatus of the associative array type includes a first memory, a second memory that stores a value, and a third memory. The first memory stores a key and an address of the second memory. The address of the second memory is an address where the value corresponding to the key is stored. The third memory stores an address of the first memory. The address of the first memory is an address where the key corresponding to the value stored in the second memory is stored. The first memory further stores a flag that indicates whether or not the key has been registered.

A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency f.sub.s, operate in accordance with a clock having a frequency f.sub.s×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency f.sub.D×M, decimates data at the sampling frequency f.sub.s input from the integration calculation unit (10) in the last stage at a sampling frequency f.sub.D, and delays data obtained as a result of decimation by (M−1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency f.sub.D×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samples before.

A method for processing a bitstream starts by shifting a bitstream of a first sample of a signal into a buffer. The buffer also holds bits of one or more additional bitstreams for one or more additional samples of the signal. Bits of a first half of the buffer are incrementally compared to corresponding bits of a second half of the buffer. Each bit of the first half of the buffer is compared to a corresponding bit of the second half of the buffer. A computation is performed on each bit of the first half of the buffer that is equal to a corresponding bit of the second half of the buffer. The results of the computations are summed to determine an output value for the first sample of the signal.

A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency f.sub.s, operate in accordance with a clock having a frequency f.sub.sM, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency f.sub.DM, decimates data at the sampling frequency f.sub.s input from the integration calculation unit (10) in the last stage at a sampling frequency f.sub.D, and delays data obtained as a result of decimation by (M1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency f.sub.DM, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samples before.

A computer-implemented method of performing an operation on an array of values at a processing unit so as to perform a phase of the operation. For each of one or more one-dimensional sequences of values of the array of values a respective section of values of the one-dimensional sequence of values is assigned to each of a plurality of threads, and a first thread of the plurality of threads determines at least one contribution, from the section of values assigned to the first thread, to the phase of the operation that is to be completed by a second thread of the plurality of threads for a neighbouring section of values of the one-dimensional sequence of values. The at least one contribution is written to a memory, and a second thread of the plurality of threads reads the at least one contribution from the memory. and completes the phase of the operation for the neighbouring section of values assigned to the second thread in dependence on the at least one contribution read from the memory in order to generate a section of processed values.

A separable operation on a two-dimensional array of values is performed at a processing unit. A two-dimensional array of values is divided into a plurality of sub-arrays of values. An initial phase of the separable operation is performed for a sub-array to generate a processed value for each value of the sub-array. Threads write a first plurality of processed values to the memory over a plurality of writing steps. Each of the threads reads a second plurality of processed values from the memory over a plurality of reading steps. A subsequent phase of the separable operation is performed for the processed values read by the threads to generate an output value for each value of the sub-array in a transposed position; wherein a respective processed value is written into each of the memory banks of the memory in at least one of the writing steps, and a respective processed value is read from each of the memory banks of the memory in at least one of the reading steps.

A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency f.sub.S that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency f.sub.S to reduce the sampling frequency f.sub.S to a sampling frequency f.sub.D=f.sub.S/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency f.sub.D and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples.

A method, apparatus, and computer program product for calculating a sampled signal are disclosed. A method in accordance with the disclosure may include determining discrete samples of a continuous signal having a finite spectrum and using a function series expansion to calculate at least a portion of the continuous signal over the discrete samples. In accordance with some embodiments, an original signal may be calculated over discrete samples with arbitrary accuracy. Polyphase filtering is not used in some embodiments. Some embodiments can be used for arbitrary, including irrational, variation of the sampling rate of the signal with a bounded spectrum. Some embodiments provide for much faster calculation than direct application of the Kotelnikov (Nyquist-Shannon) theorem. In some embodiments, the calculation may be performed according to the disclosed theorem but, instead of discrete signal convolutions with kernels having different phases, a function series expansion may be used.

A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency f.sub.S that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency f.sub.S to reduce the sampling frequency f.sub.S to a sampling frequency f.sub.D=f.sub.S/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency f.sub.D and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency f.sub.D and subtract, from the input data, data preceding the input data by a plurality of samples.