A processing method in a wireless telecommunications receiver receiving a digitally modulated single-carrier signal includes, between a matched filter, in the time domain, operating at a frequency drx×B and a frequency equalizer, operating at the frequency B, a decimation step comprising: i/extracting, from a filtered signal frame, a first sequence of samples for aiding the decimation and having the same power; and a second sequence of payload samples intended to be equalized; ii/estimating the variance in the power of each of the drx decimation phases of the first sequence and identifying the n.sup.th decimation phase associated with the minimum variance; iii/decimating the second sequence by selecting the n.sup.th decimation phase of the second sequence and supplying the decimation phase at the input of the frequency equalizer.

A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

An analysis filter bank corresponding to multiple sub-bands, which performs frequency-division filtering on an input signal to generate multiple sub-band signals, the analysis filter bank comprising: a sub-band response pre-compensator which performs a linear filtering on the input signal to generate a response pre-compensated signal, multiple sub-filters with different central frequencies, which perform complex-type first-order infinite impulse response filtering respectively on the response pre-compensated signal to generate multiple sub-filter signals, and multiple binomially-combining and rotating devices based on a set of binomial weights, each of which performs a weighted summation on at least two of the sub-filter signals with the set of binomial weights, and rotates a weighted-summation result with a rotating phase according to a corresponding sub-band central frequency to generate one of the sub-band signals, wherein the at least two of the sub-filter signals are generated by at least two of the sub-filters adjacent in central frequency.

A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low pass filter is presented. The filter utilizes history capacitor arrays incorporating banks of capacitors. A linear interpolation technique is used in the IIR filter with second order antialiasing filtering, whose transfer function is sinc(x).sup.2 per stage. It also uses a g.sub.m cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7.sup.th-order charge-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of the filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

In accordance with an embodiment, a digital microphone interface circuit includes a delta-sigma analog-to-digital converter (ADC) having an input configured to be coupled to a microphone, a digital lowpass filter coupled to an output of the delta-sigma ADC, and a digital sigma-delta modulator coupled to an output of the digital lowpass filter. The delta-sigma ADC, the digital lowpass filter, and the digital sigma-delta modulator are configured to operate at different sampling frequencies.

A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low pass filter is presented. The filter utilizes history capacitor arrays incorporating banks of capacitors. A linear interpolation technique is used in the IIR filter with second order antialiasing filtering, whose transfer function is sinc(x).sup.2 per stage. It also uses a g.sub.m cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7.sup.th-order charge-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of the filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

A method for compensating the bandedge ripple of an analog filter, using a circuit comprising a low pass filter is described. The method comprises receiving, at the analog filter, a plurality of tones of different frequencies from a tone generator, measuring, an amplitude of each tone in the plurality of tones after each tone is processed by the analog filter, storing the measured amplitudes and frequencies in a database, measuring a bandedge ripple by measuring a difference in amplitude between a first tone and a second tone from the plurality of tones, and selecting a low pass filter, from a plurality of low pass filters, based on the measured difference.

In accordance with an embodiment, a digital microphone interface circuit includes a delta-sigma analog-to-digital converter (ADC) having an input configured to be coupled to a microphone, a digital lowpass filter coupled to an output of the delta-sigma ADC, and a digital sigma-delta modulator coupled to an output of the digital lowpass filter. The delta-sigma ADC, the digital lowpass filter, and the digital sigma-delta modulator are configured to operate at different sampling frequencies.