A method of increasing the sample rate of a digital signal by creating intermediate sample points between adjacent neighbouring sample points comprising the step of populating each of the intermediate sample points depending on a weighted influence of a predetermined number of the neighbouring sample points, the weighted influence being calculated by representing the digital signal or filter at the predetermined number of sample points at least in part by its cosine components, which are each represented by absolute values of a cosine function in the time domain substantially limited to half a waveform cycle at its mid-point; combining the aforementioned cosine components at each of the neighbouring sample points to obtain waveforms at each of the neighboring sample points; determining values for each of the waveforms at the intermediate sample points and combining the determined values at the intermediate sample point to derive the weighted influence.

A discrete-time (e.g., digital) filter can be used as an interpolation filter for processing an oversampled input signal, such as included as a portion of a sigma-delta digital-to-analog conversion circuit. An interpolation filter control circuit can be configured to adjust a filter order of the discrete-time interpolation filter at least in part in response to information indicative of an envelope signal magnitude. For example, higher-level input signals might be processed using an interpolation filter having a stop-band attenuation that is more stringently-specified (e.g., having greater attenuation) than a corresponding attenuation used for lower-level input signals. The filter order can be variable, such as varied in response to a detected envelope magnitude of the input signal to achieve power savings as compared to a filter having fixed parameters.

Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second adder operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multistage topology, a register is disposed between each stage and clocked to reduce ripple power.

A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate f.sub.S for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate f.sub.samp, the first clock rate f.sub.S being N times greater than the second clock rate f.sub.samp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate f.sub.samp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

A method of increasing the sample rate of a digital signal by creating intermediate sample points between adjacent neighbouring sample points comprising the step of populating each of the intermediate sample points depending on a weighted influence of a predetermined number of the neighbouring sample points, the weighted influence being calculated by representing the digital signal or filter at the predetermined number of sample points at least in part by its cosine components, which are each represented by absolute values of a cosine function in the time domain substantially limited to half a waveform cycle at its mid-point; combining the aforementioned cosine components at each of the neighbouring sample points to obtain waveforms at each of the neighboring sample points; determining values for each of the waveforms at the intermediate sample points and combining the determined values at the intermediate sample point to derive the weighted influence.

A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate f.sub.S for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate f.sub.samp, the first clock rate f.sub.S being N times greater than the second clock rate f.sub.samp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate f.sub.samp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

The present invention relates to a digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency. The interpolator comprises a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage.