Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

The invention relates to methods for the conversion of data, which comprises at least the following steps. A number of asynchronously incoming data packets (P0, P1 . . . . P4) is received, wherein the data packets (DP) comprise input data (ED) with a first sample rate. The input data (ED) are assigned to positions in a filter buffer (22) based on the first sample rate. The input data (ED) are combined in the filter buffer (22) based on their respective position to form output data (SKD) with a defined second sample rate (SR2) in in course of a low-pass filtering (23). In the process the input data advance in the filter buffer (22) on a position-by-position and data-driven basis. The invention further relates to a conversion device (20) and a system (30) for the transmission of data as well as to the use of a filter buffer (22) in a conversion device (20) for the conversion of sample rates (SR1, SR2).

The present document relates to the design of anti-aliasing and/or anti-imaging filters for resamplers using rational resampling factors. In particular, the present document relates to a method for implementing such anti-aliasing and/or anti-imaging filters with reduced computational complexity. In addition, the present document relates to further aspects of an audio encoding and decoding system, such as the phase relation between the channels of a multi-channel audio signal and/or the structure of the bitstream of an encoded audio signal.