A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the multiplying factor adjustment value.

A filter circuit includes a processor configured to compare a current input value with a last-time output value, add a first correction value to the current input value and to the last-time output value if a comparison result between the current input value and the last-time output value is greater than a predetermined value, and add a second correction value smaller than the first correction value to the current input value and to the last-time output value if the comparison result is smaller than or equal to the predetermined value, and calculate a current output value based on the current input value and the last-time output value to each of which the first correction value or the second correction value has been added.

A method includes receiving an input digital signal and applying the input digital signal to digital filter processing with a corner frequency to produce a filtered output digital signal. The digital filter processing includes a set of multiplication operations using a set of filter multiplication coefficients. The set of multiplication operations is performed by alternately using a first set of approximate multiplication coefficients and a second set of approximate multiplication coefficients different from the first set of approximate multiplication coefficients. The approximate multiplication coefficients in the first set of approximate multiplication coefficients and the second set of approximate multiplication coefficients approximate multiplication coefficients in the set of filter multiplication coefficients as a function of negative power-of-two values. The alternating of multiplication operations results in digital filter processing with average corner frequency approximating the corner frequency.

Data output from each of the n delay elements and a remainder value output from a divider in the previous calculation are input to an adder, and an addition process for obtaining a total sum thereof is executed. In addition, a division process is performed by dividing the total sum output from the adder by n, and a quotient and a remainder are output from the divider. The remainder is delayed by a remainder delay element by one clock, is output to the adder, and is added in the next calculation.

A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the multiplying factor adjustment value.

A method includes receiving an input digital signal and applying the input digital signal to digital filter processing with a corner frequency to produce a filtered output digital signal. The digital filter processing includes a set of multiplication operations using a set of filter multiplication coefficients. The set of multiplication operations is performed by alternately using a first set of approximate multiplication coefficients and a second set of approximate multiplication coefficients different from the first set of approximate multiplication coefficients. The approximate multiplication coefficients in the first set of approximate multiplication coefficients and the second set of approximate multiplication coefficients approximate multiplication coefficients in the set of filter multiplication coefficients as a function of negative power-of-two values. The alternating of multiplication operations results in digital filter processing with average corner frequency approximating the corner frequency.

Data output from each of the n delay elements and a remainder value output from a divider in the previous calculation are input to an adder, and an addition process for obtaining a total sum thereof is executed. In addition, a division process is performed by dividing the total sum output from the adder by n, and a quotient and a remainder are output from the divider. The remainder is delayed by a remainder delay element by one clock, is output to the adder, and is added in the next calculation.