A phase shifter includes a signal input, a signal output, an ESD protection circuit, first and second signal paths between the signal input and the signal output. The ESD protection circuit includes first and second two port devices, each two port device being switchable between a high impedance state and a low impedance state. The first signal path includes the first two port device of the ESD protection circuit and a first delay line configured to provide a first phase shift to a signal transmitted from the signal input to the signal output via the first signal path. The second signal path includes the second two port device of the ESD protection circuit and a second delay line configured to provide a second phase shift, different from the first phase shift, to the signal transmitted from the signal input to the signal output via the second signal path.

A phase shifter includes a signal input, a signal output, an ESD protection circuit, first and second signal paths between the signal input and the signal output. The ESD protection circuit includes first and second two port devices, each two port device being switchable between a high impedance state and a low impedance state. The first signal path includes the first two port device of the ESD protection circuit and a first delay line configured to provide a first phase shift to a signal transmitted from the signal input to the signal output via the first signal path. The second signal path includes the second two port device of the ESD protection circuit and a second delay line configured to provide a second phase shift, different from the first phase shift, to the signal transmitted from the signal input to the signal output via the second signal path.

Apparatus and associated methods relate to a low-noise wideband active phase shifter. The low-noise wideband active phase shifter includes first and second transconductance cells, a fixed LC series network and a tunable LC series network configured to form an all-pass lattice network. The first and second transconductance cells, each include a transistor, a feedback network, and a transistor biasing network. The transistor has an input terminal and an output terminal. The negative feedback network electrically couples the input and output terminals of the transistor. The biasing network provides input and output biasing of the transistor. The fixed LC series network connects between the first and the second transconductance cells. The tunable LC series network connects between the first and the second transconductance cells.

Apparatus and associated methods relate to a low-noise wideband active phase shifter. The low-noise wideband active phase shifter includes first and second transconductance cells, a fixed LC series network and a tunable LC series network configured to form an all-pass lattice network. The first and second transconductance cells, each include a transistor, a feedback network, and a transistor biasing network. The transistor has an input terminal and an output terminal. The negative feedback network electrically couples the input and output terminals of the transistor. The biasing network provides input and output biasing of the transistor. The fixed LC series network connects between the first and the second transconductance cells. The tunable LC series network connects between the first and the second transconductance cells.

The present disclosure is directed to a coil unit decoupling apparatus and a magnetic resonance system. The apparatus is connected to a first coil unit and a second coil unit in a magnetic resonance system, and is configured to separate, by using a distribution characteristic of a spatial quadrature field between the first coil unit and the second coil unit, a Helmholtz signal and an anti-Helmholtz signal from signals received from the first coil unit and the second coil unit, so as to implement decoupling between the first coil unit and the second coil unit. This facilitates the complexity of decoupling coil units being reduced.

A phase shifter includes: a first all-pass filter; a second all-pass filter; a first switching switch to provide a signal to either one of the first all-pass filter and the second all-pass filter; and a second switching switch to select the signal having passed through the first all-pass filter or the signal having passed through the second all-pass filter, wherein the first all-pass filter includes two inductors and three capacitors, and the second all-pass filter includes two inductors and three capacitors, or the first all-pass filter includes three inductors and two capacitors, and the second all-pass filter includes three inductors and two capacitors, and element values of elements included in the first all-pass filter and element values of elements included in the second all-pass filter are determined by impedance at which impedance matching is achieved, a frequency of the signal, and a variable.

Carrier aggregation circuit having multi-stage filter combination. In some embodiments, a carrier aggregation circuit can include a first combining stage configured to aggregate a first signal in a first path associated with a first band and a second signal in a second path associated with a second band to provide a first aggregated signal in a first combined path. The carrier aggregation circuit can further include a second combining stage configured to aggregate the first aggregated signal in the first combined path and a third signal in a third path associated with a third band to provide a second aggregated signal in a second combined path.

A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.

A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.

The present invention discloses an ultra wide band digital phase shifter, wherein the phase shifter includes a coupler, a first impedance network and a second impedance network. The coupler is cascaded by spiral inductor coupling units; each stage of spiral inductive coupling unit includes a first spiral inductor and a second spiral inductor coupled mutually; multistage cascade of the spiral inductor coupling units is implemented through the series connection of each stage of first spiral inductors and the series connection of each stage of second spiral inductors; and the coupling interval or microstrip band width of each stage of spiral inductor coupling unit in the coupler from the exterior to the interior decreases gradually. The impedance networks are implemented using LC circuits and switching elements, and the states of the impedance networks are switched by a switch, thus producing phase displacement; therefore, the impedance network is rational in structure and is easy to implement; the phase shifter has the advantages of compact structure, small area occupation and good wideband character and has larger advantages and application space in integrated chip applications.