A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.

Provided is a compact digital attenuator. The compact digital attenuator includes a first attenuation cell to an nth attenuation cell, which include a plurality of attenuation cells connected to each other in parallel through a transmission line, wherein each of the plurality of attenuation cells may include a plurality of switch elements connected to each other in parallel, wherein the plurality of switch elements may be connected to the transmission line through one contact point.

Provided is a compact digital attenuator. The compact digital attenuator includes a first attenuation cell to an nth attenuation cell, which include a plurality of attenuation cells connected to each other in parallel through a transmission line, wherein each of the plurality of attenuation cells may include a plurality of switch elements connected to each other in parallel, wherein the plurality of switch elements may be connected to the transmission line through one contact point.

The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.

According to an embodiment, a high frequency integrated circuit includes a signal splitter, an attenuator, a first conductive element, and first to eighth switches. The signal splitter receives a high frequency signal at an input terminal, splits the high frequency signal to two lines, and outputs the signals split into the two lines from a first output terminal and a second output terminal. The attenuator has multiple amounts of attenuation values. In the first conductive element, a first amount of attenuation is set. The high frequency integrated circuit outputs a plurality of output signals having different gain values from the first high frequency output terminal and the second high frequency output terminal, respectively.

An attenuator is configured to attenuate and phase-shift a radiofrequency signal according to a control signal, having a plurality of first attenuation cells (A.sub.1, A.sub.N−1), configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular bit of the control signal, and implementing a combinatorial logic on the bits of the control signal that are used to control the first attenuation cells, and at least one second attenuation cell (B.sub.1, B.sub.M) configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular output implementing the combinatorial logic. A control node is also provided for an array antenna having such an attenuator, and an array antenna having an array of such control node and a satellite.

An attenuator is configured to attenuate and phase-shift a radiofrequency signal according to a control signal, having a plurality of first attenuation cells (A.sub.1, A.sub.N−1), configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular bit of the control signal, and implementing a combinatorial logic on the bits of the control signal that are used to control the first attenuation cells, and at least one second attenuation cell (B.sub.1, B.sub.M) configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular output implementing the combinatorial logic. A control node is also provided for an array antenna having such an attenuator, and an array antenna having an array of such control node and a satellite.

Differential attenuation circuitry, including: first and second input nodes; first and second output nodes; and an impedance network connected between the first and second input nodes and the first and second output nodes to provide a differential output voltage signal between the first and second output nodes which is attenuated compared to a differential input voltage signal applied between the first and second input nodes, wherein the impedance network includes: a common-mode node; a first impedance network connected between the first input node, the common-mode node and the first output node; and a second impedance network connected between the second input node, the common-mode node and the second output node, and wherein the differential attenuation circuitry further includes: an input-to-input path comprising one or more impedances and one or more switches connected between the first and second input nodes to provide a current path independent of the common-mode node.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.