The present invention relates to pulse power technology. The system includes an input channel, a pulse edge detector (2) connected in series with two inputs, a filter (3), a variable delay unit (4), and a feedback channel from the generator to one of the inputs of the pulse edge detector (2). The system comprises a reference delay unit (1), and the input channel is connected both to the variable delay unit (4) and to a reference delay unit (1) for simultaneous supply of input to said units. Signals to both inputs of the pulse edge detector (2) are synchronous on average, i.e. tstab.avg=1/τ∫ tstab dt=tref with τ>>τest.oper where: tstab.avg—generator output delay relative to the input signal, averaged over the operation time of the system τ at a given tref; tref—reference unit (1) output delay relative to the input signal; τest.oper—stabilization system time response to changes in external parameters, with the stabilization delay tstab determined from the condition tstab=tvar+tunstab where: tvar—delay of the variable delay unit (4); tunstab—unstable delay of the generator. The stabilization of the delay is independent of the pulse repetition frequency.

Techniques are provided for automatic gain control processing to reduce adverse effects associated with clipped samples resulting from conversion of analog signals to digital signals. A methodology according to an embodiment includes identifying a clipped sample of the digital signal, for example by comparison of the digitized sample values to a threshold value associated with a full scale value of the converter. The method also includes applying a window function to portions of the digital signal. The window function is configured to attenuate samples of the digital signal within a region centered on the identified clipped sample. A Hilbert finite impulse response (FIR) filter may be applied to the digital signal prior to applying the window function. Parameters of the window function are selected based on frequency response characteristics of the FIR filter and on signal to noise ratio requirements of an application that receives the windowed digital signal.

Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include L N-tap decision feedback equalizer (DFE) branch input lines and an unfolding multiplexer array network. The network is configured to generate at least one unfolded output based on inputs from a subset of the branch input lines and includes a plurality of multiplexer arrays wherein outputs from a first multiplexer array in the plurality of multiplexer arrays are connected to selection lines of a second multiplexer array in the plurality of multiplexer arrays.

A power supply includes an inverter configured to convert direct current (DC) power into alternating current (AC) power, an impedance matching circuit configured to supply the AC power to a load, and a controller configured to detect a delay time of an output voltage and an output current output to the impedance matching circuit and the load and to adjust a frequency of the output voltage according to the detected delay time.

A power supply includes an inverter configured to convert direct current (DC) power into alternating current (AC) power, an impedance matching circuit configured to supply the AC power to a load, and a controller configured to detect a delay time of an output voltage and an output current output to the impedance matching circuit and the load and to adjust a frequency of the output voltage according to the detected delay time.

An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

A data receiver includes a plurality of samplers, each of the samplers amplifies a difference between a first reference voltage and an input voltage and amplifies a difference between a second reference voltage and the input voltage. Operational paths of the samplers are differently controlled according to a level of second data corresponding to the second reference voltage, and first data corresponding to the first reference voltage is past data preceding current data and the second data is past data preceding the first data in the sampler.

A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

A method for equalizing a signal comprising modulated symbols comprising a block of N received symbols comprises: demultiplexing the N received symbols by factor L to generate a predetermined number L of sub-blocks of symbols, each comprising a version of the N received symbols sub-sampled by factor L, the independent equalization of each sub-block using an identical equalization algorithm, multiplexing the equalized symbols of each sub-block to obtain a block of N equalized symbols, removing instances of interference linked to paths other than two paths of higher power comprising generating an interference term resulting from the influence, on the equalized symbols, of all paths of the channel having the impulse response of the transmission channel except two paths of higher power, subtracting the interference term from the symbols of the block of N received symbols, and, a second equalization step equal to a second iteration of the first equalization step.