Patent classifications
H03H7/325
DELAY CIRCUIT FOR TIME OFFSETTING A RADIOFREQUENCY SIGNAL AND INTERFERENCE REDUCING DEVICE USING SAID CIRCUIT
A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.
Controlled large signal capacitor and inductor
An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.
Microelectromechanical tunable delay line circuit
Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.
Microelectromechanical Tunable Delay Line Circuit
Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.
Clock recovery based on digital signals
A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.
CLOCK RECOVERY BASED ON DIGITAL SIGNALS
A clock recovery circuit includes a first pulse circuit, a second pulse circuit, a state change circuit connected to the first pulse circuit and the second pulse circuit and a first delay circuit connected to the state change circuit and each of the first pulse circuit and the second pulse circuit. The first pulse circuit receives data inputs to generate a first pulse signal. The second pulse circuit receives the data inputs to generate a second pulse signal. The state change circuit receives the first pulse signal and the second pulse signal and generate a first clock signal for a first transition of one of the data inputs in a first unit interval (UI). The first delay circuit receives the generated first clock signal and mask other transitions of the data inputs in the first UI.
Resonator and resonating method
A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.
RESONATOR AND RESONATING METHOD
A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.
Methods and apparatus of adjusting delays of signals
In some examples, a delay apparatus includes a controllable delay line comprising a plurality of delay elements selectively connected in a signal path to vary a delay of a signal passing through the delay line, and a controllable phase shifter comprising reflective loads adjustable to vary a phase shift applied to the signal.
Resonator and resonating method
A resonator and resonator method are provided. The resonator includes an inductor, a capacitor, and a switch configured to maintain energy in at least one of the inductor and the capacitor for a select period of time and to enable variability of energy in the at least one of the inductor and the capacitor for another period of time, to set a resonating frequency of the inductor and the capacitor.