A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

A drive circuit includes a first driver to control on/off of an upper arm, a second driver to control on/off of a lower arm, a first switching device including a first terminal connected with a power supply for the first driver, a second terminal connected with a power supply for the second driver and a control terminal, a booster circuit to turn on the first switching device by boosting a control signal which is at a high level when the lower arm is in an on state, a second switching device to cause continuity between the control terminal and the booster circuit when the control signal is at the high level, and first switch unit to short-circuit the control terminal and the terminal for grounding when the control signal is at the low level.

A radio frequency (RF) switch includes a switchable RF path including a plurality of transistors coupled in series; a gate bias network including a plurality of resistors, wherein the gate bias network is coupled to each of the plurality of transistors in the switchable RF path; and a bypass network including a first plurality of transistors coupled in parallel to each of the plurality of transistors in the switchable RF path and a second plurality of transistors coupled in parallel to each of the plurality of resistors in the gate bias network.

A frequency-locked circuit for a variable frequency topology is configured to trigger a Pulse Width Modulation (PWM) controller to lock a frequency of a driving signal outputted by the PWM controller. The frequency-locked circuit includes an AC wave generating circuit and a comparator. The AC wave generating circuit receives and converts the driving signal to generate an AC wave signal. The comparator is electrically connected to the AC wave generating circuit and receives the AC wave signal. The comparator compares the AC wave signal with a reference signal to generate a comparison output signal. In response to determining that the AC wave signal is greater than the reference signal, the comparison output signal triggers the PWM controller to convert the driving signal from one voltage level to another voltage level so as to lock the frequency. The one voltage level is different from the another voltage level.

A gate drive circuit according to an embodiment includes: a voltage detector that detects a voltage between a first terminal and a second terminal of a switching device; a delay circuit that outputs, with a delay for a predetermined time, a detected value of the voltage obtained from the voltage detector; and a first off-mode drive circuit and a second off-mode drive circuit that apply a control signal to a control terminal of the switching device for turning off the switching device, wherein the first off-mode drive circuit turns off the switching device faster than the second off-mode drive circuit, and stops its operation to turns off the switching device when the delayed voltage value output from the delay circuit exceeds a predetermined threshold value.

A switching component and switch assembly. The switching component comprises a first control node, a common node, a plurality of intermediate nodes, a second control node, and a capacitive node; a plurality of transistors connected in series between the control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors, each transistor of the plurality of transistors having a gate coupled to the second control node; and a plurality of capacitive components, one capacitive component being coupled between each intermediate node and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each intermediate node, the capacitive component is configured to accrue an opposite charge to the transistors.

An electrical switching system includes a constant-power controller and a switching device electrically coupled between a first node and a second node. The constant-power controller is configured to (a) generate a digital control signal to control the switching device, (b) control a duration of an active phase of the digital control signal at least partially based on a voltage across the switching device, and (c) control a peak value of the digital control signal to regulate a peak magnitude of current flowing through the switching device.

A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

An electronic device includes an internal voltage driving circuit configured to drive an internal voltage to one of first and second power supply voltages based on a driving control signal depending on an operating frequency. The electronic device includes a driving control signal generation circuit configured to generate the driving control signal that sets a level of the internal voltage, by detecting the level of the internal voltage.