A differential switch circuit includes: a first transistor having a first terminal coupled with a first input terminal, a second terminal coupled with a first output terminal, and a control terminal coupled with a switch signal receiving terminal; a second transistor having a first terminal coupled with a second input terminal, a second terminal coupled with a second output terminal, and a control terminal coupled with the switch signal receiving terminal; a central switch element positioned between the control terminals of the first and second transistors; and a switch element control circuit for controlling the central switch element based on a switch signal. When the switch signal turns on the first and second transistors, the switch element control circuit turns off the central switch element, and when the switch signal turns off the first and second transistors, the switch element control circuit turns on the central switch element.

An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A circuit for quenching an avalanche photodiode (APD) detector is disclosed herein. The circuit may comprise a discrete transistor configured to draw a quench current so as to enable a drop in a reverse bias voltage applied to the APD detector, and an integrated circuit connected to the discrete transistor, the integrated circuit including a plurality of circuit elements for controlling the reverse bias voltage.

A circuit for quenching an avalanche photodiode (APD) detector is disclosed herein. The circuit may comprise a discrete transistor configured to draw a quench current so as to enable a drop in a reverse bias voltage applied to the APD detector, and an integrated circuit connected to the discrete transistor, the integrated circuit including a plurality of circuit elements for controlling the reverse bias voltage.

One example includes a switch system. The system includes a first signal port and a second signal port. The system also includes a first switching path arranged between the first and second signal ports. The first switching path includes at least one first switch and at least one of the at least one first switch being configured as a high-speed switching device. The system further includes a second switching path arranged between the first and second signal ports in parallel with the first switching path. The second switching path includes at least one second switch and at least one of the at least one second switch being configured as a high-performance switching device.

A lidar system identifies anomalous optical pulses received by the lidar system. The lidar system includes a light source configured to output a plurality of transmitted pulses of light, each transmitted pulse of light having one or more representative characteristics, a scanner configured to direct the plurality of transmitted pulses of light to a plurality of locations within a field of regard, and a receiver configured to detect a plurality of received pulses of light from the field of regard. The lidar system is configured to identify an anomalous pulse amongst the plurality of received pulses of light based on its having at least one characteristic that does not correspond to the one or more representative characteristics of the plurality of transmitted pulses of light.

A lidar system identifies anomalous optical pulses received by the lidar system. The lidar system includes a light source configured to output a plurality of transmitted pulses of light, each transmitted pulse of light having one or more representative characteristics, a scanner configured to direct the plurality of transmitted pulses of light to a plurality of locations within a field of regard, and a receiver configured to detect a plurality of received pulses of light from the field of regard. The lidar system is configured to identify an anomalous pulse amongst the plurality of received pulses of light based on its having at least one characteristic that does not correspond to the one or more representative characteristics of the plurality of transmitted pulses of light.