Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.

A driving device includes a voltage regulator, a voltage generator, and a first NMOSFET. The voltage regulator is coupled between a first high-voltage terminal and the output terminal of the driving device. The voltage regulator receives the first high voltage of the first high-voltage terminal. The voltage regulator steps down the first high voltage to generate a supply voltage. The voltage generator is coupled to a second high-voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage for the output terminal of the driving device. The reference voltage is substantially lower than the supply voltage. The first NMOSFET is coupled between the output terminal of the driving device and a low-voltage terminal.

A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.

Pre-conditioning circuitry for pre-conditioning a node of a circuit to support a change in operation of the circuit, wherein the circuit is operative to change a state of the node to effect the change in operation of the circuit, and wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge directly to the node to reduce the magnitude of the change to the state of the node required by the circuit to achieve the change in operation of the circuit.

A gate driver circuit includes a pulse generator that receives an input signal and generates a pulse signal in response to a switch-on command included in the input signal. The pulse signal has a pulse with a pulse length that is dependent on a level of a pulse control signal. The circuit further includes a sampling circuit that samples an output voltage subsequent to the pulse and stores a respective sampled value, and a controller that receives the sampled value of the output voltage and a reference voltage and updates the level of the pulse control signal based on the sampled value and the reference voltage. A driver circuit generates the output voltage based on the pulse signal.

Aspects of the invention relate to a high-power switching module for the direct pulse energy feeding of a consumer with a plurality of switching stages connected in series. A coupling element and an energy buffer store are provided, the coupling element coupling a primary circuit comprising a balancing capacitance and a semiconductor switch to a secondary circuit comprising the energy buffer store, the coupling element being provided and embodied for obtaining energy of the balancing capacitance and delivering this energy to the energy buffer store during the on phase of the semiconductor switch, and the energy buffer store being provided and embodied for delivering the obtained energy to an energy store of the driver assembly when the semiconductor switch is in the switched-off state.

A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Low-leakage switch circuit techniques to reduce leakage current of an off-state switch, while maintaining a low on-resistance. The low-leakage switch circuit may allow measurement of low current signals in a transimpedance amplifier with improved accuracy without, the need for calibration. The low-leakage switch circuit may include a bootstrapping path connecting two or more terminals or voltage nodes of an off-state switch in the switch circuit. The bootstrapping path is configured to bootstrap major leakage current contributors in the switch circuit, such as the substrate diode leakage, the subthreshold leakage, or combinations thereof.